公开(公告)号：US20240281433A1

公开(公告)日：2024-08-22

申请号：US18652848

申请日：2024-05-02

Applicant: Mohan Kumar JINDAL ,  Shailja JINDAL

Inventor： Mohan Kumar JINDAL ,  Ashish Shridhar JADHAO ,  Sumit Manoj KAVATHEKAR ,  Shon Pravin TAWARE ,  Adithi L ,  Ravindra Madan LANDE ,  Sesha Sowjanya BATTULA

IPC: G06F16/23 ,  G06F16/2455

CPC classification number: G06F16/2386 ,  G06F16/2365 ,  G06F16/2455

Abstract: Disclosed is a device (106) for bulk-only transfer of data including a query unit (110) and a control unit (112). The query unit (110) is configured to configure the second device (104) based on the set of descriptors received from the first device (102). The control unit (112) identifies a direction of transfer of data between the first device (102) and the second device (104), determines a status of a bulk-input endpoint (120) and a bulk-output endpoint (122) for the transfer of the data between the first device (102) and the second device (104), transfers the plurality of CBWs to the first device (102) and transfers the data between the first device (102) and the second device (104) based on the identified direction.

公开(公告)号：US20240380733A1

公开(公告)日：2024-11-14

申请号：US18652835

申请日：2024-05-02

Applicant: Mohan Kumar JINDAL ,  Shailja JINDAL

Inventor： Mohan Kumar JINDAL ,  Srirama Chandra Murthy PRATAPA ,  Vidya Milind KULKARNI ,  Pratiksha Balasaheb PAWAR ,  Dhileep Kumar PAILU ,  Sreehari KAMSALA ,  Anju VARGHESE ,  Hari Prasad BADHAM ,  Ayush Rushat Venkata ARIPIRALA ,  Ujjwal BAJAJ ,  Sumit Manoj KAVATHEKAR ,  Akshay Purushottam SONI ,  Jaspritam SINGH ,  Sanchith Vakkalaganti MAHESH ,  Mayuri Uday Dawande ,  Pratiksha Ishwar JONDHALE ,  Sahana m KULKARNI ,  Ravi PATEL

IPC: H04L9/40

Abstract: Disclosed is a data diode configured to receive a user-defined set of values for a set of parameters from the user device, generate a filter logic based on the user-defined set of values, receive one or more data packets and a set of values for the set of parameters corresponding to each data packet of the one or more packets from the plurality of transmitter devices, segregate the one or more data packets into a set of valid data packets and a first set of invalid data packets, transmit the set of valid data packets to the plurality of receiver devices, and store the first set of invalid data packets with a first set of time-stamped invalidity logs the data diode enables unidirectional flow of the set of valid data packets from the plurality of transmitter devices to the plurality of receiver devices.

公开(公告)号：US20240291647A1

公开(公告)日：2024-08-29

申请号：US18652844

申请日：2024-05-02

Applicant: Mohan Kumar JINDAL ,  Shailja JINDAL

Inventor： Mohan Kumar JINDAL ,  Srirama Chandra Murthy PRATAPA ,  Sumit Manoj KAVATHEKAR ,  Ashish Shridhar JADHAO ,  Jaspritam SINGH ,  Sanchith Vakkalaganti MAHESH ,  Mayuri Uday DAWANDE ,  Pratiksha Ishwar JONDHALE ,  Shon Pravin TAWARE ,  Adithi L ,  Ravindra Madan LANDE ,  Sesha Sowjanya BATTULA ,  Akanksha Kishor BEDEKAR ,  Rakshanda Baban TIDKE ,  SaiRangesh THIRUNAGARAM ,  Kanan Subramanium NADAR ,  Swapnil Sopanrao MORE ,  Nikunj Mukeshbhai VAGHANI ,  Sahana NAZAR ,  Sravani RANAM ,  Jeevan Kumar Reddy PALAGANI ,  Hari Prasad BADHAM ,  Dinesha SHIVANGOUDRA ,  Achyuth Goud YESU ,  Sai Charan PERUMALLA ,  Vamsi Krishna KANUMURI

IPC: H04L9/08 ,  G06F21/31

CPC classification number: H04L9/0877 ,  G06F21/31

Abstract: Disclosed is a data processing apparatus (104) including a key memory (123) to store a list of cryptography keys, a key USB subunit (132) to enable receiving one or more cryptography keys from a user to generate an updated list of cryptography keys, a cryptography unit (122) to encrypt first data to generate second data based on a cryptography key randomly selected from the updated list of cryptography keys, and decrypt the second data to generate the first data, based on the key, and a USB subunit (130) to enable exchange of the first data between a first external device (104) and the cryptography unit (122), and the second data between a second external device (106) and the cryptography unit (122). The data processing apparatus (102) is implemented on at least one of, a Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuits (ASICs).