公开(公告)号：US5235536A

公开(公告)日：1993-08-10

申请号：US762348

申请日：1991-09-19

申请人： Noritsugu Matsubishi ,  Yoshio Tokuno ,  Hiroshi Masaki ,  Masato Yamazaki

发明人： Noritsugu Matsubishi ,  Yoshio Tokuno ,  Hiroshi Masaki ,  Masato Yamazaki

IPC分类号： G06F7/505 ,  G06F7/53 ,  G06F7/533 ,  G06F7/544 ,  G06F7/57 ,  G06F15/80 ,  G06F17/16

CPC分类号： G06F7/57 ,  G06F17/16 ,  G06F7/544 ,  G06F7/5443 ,  G06F2207/5442

摘要： A processing unit for executing parallel cumulative absolute difference operations in a first mode, and an inner product operation in a second mode, includes an input bus group for receiving first input data, second input data, and third input data. A plurality of processor elements are coupled to the input bus group, each processor element being coupled to compute a cumulative absolute difference between the first input data and the second input data in the first mode, and to compute and accumulate one term of Booth's algorithm for multiplying the first input data by the third input data in the second mode. An output bus group is coupled to the processor elements, for receiving the terms of Booth's algorithm. An accumulator circuit is coupled to the output bus group, for shifting and adding terms of Booth's algorithm output by the processor elements.

公开(公告)号：US5216628A

公开(公告)日：1993-06-01

申请号：US732818

申请日：1991-07-19

申请人： Hideo Mizutani ,  Noritsugu Matsubishi ,  Yoshio Tokuno

发明人： Hideo Mizutani ,  Noritsugu Matsubishi ,  Yoshio Tokuno

IPC分类号： G06F7/50 ,  G06F7/544

CPC分类号： G06F7/544 ,  G06F2207/5442

摘要： An absolute value arithmetic circuit for computing the absolute value of two binary input signals, includes: a computing circuit for obtaining a difference between the two input signals, a 1's complementor for non-inverting or inverting an output from the computing circuit in accordance with a positive sign bit or a negative sign bit of the output, a priority encoder for searching an output from the 1's complementor for the position of a first "0" bit from the least significant digit of the output and delivering an encoder output indicating the position of the first "0" bit, and a bit inverting circuit for inverting and delivering a bit row from the least significant digit bit to the "0" bit in the output from the 1's complementor in accordance with the encoder output, and directly delivering a bit row from a bit higher than the "0" bit to the most significant digit bit of the output without inverting them.

摘要翻译： 用于计算两个二进制输入信号的绝对值的绝对值运算电路包括：用于获得两个输入信号之间的差的计算电路，用于根据计算电路的非反相或反相运算电路的输出的1的补码 输出的正号位或负号位，用于从输出的最低有效位搜索来自1的补码器的输出的第一“0”位的位置的优先编码器，并且传送指示位置的编码器输出 第一个“0”位，以及一个位反相电路，用于根据编码器输出从1的补码器的输出中将位行从最低有效数位位反转和传送到“0”位，并直接传送位 从高于“0”位到输出的最高有效位，而不反转它们。

公开(公告)号：US5313436A

公开(公告)日：1994-05-17

申请号：US986693

申请日：1992-12-08

申请人： Noritsugu Matsubishi

发明人： Noritsugu Matsubishi

IPC分类号： G11C11/41 ,  G11C8/18 ,  G11C11/412 ,  G11C15/04 ,  H01L27/10 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C8/18

摘要： An address transition detecting circuit which couples to a word line and an address signal line, which address signal line receives an address signal, is disclosed. The address transition detecting circuit has a word line control circuit and an address signal input circuit. The word line control circuit couples to the word line and discharges the word line. The address signal input circuit couples to the word line, the address signal line and the word line control circuit and stores an address data in response to the address signal. The address signal input circuit outputs an address transition signal to the word line in response to the address signal and the stored address data.

摘要翻译： 公开了一种地址转换检测电路，其耦合到字线和地址信号线，该地址信号线接收地址信号。 地址转换检测电路具有字线控制电路和地址信号输入电路。 字线控制电路耦合到字线并放电字线。 地址信号输入电路耦合到字线，地址信号线和字线控制电路，并响应于地址信号存储地址数据。 地址信号输入电路响应于地址信号和存储的地址数据向字线输出地址转换信号。