公开(公告)号：US09788011B2

公开(公告)日：2017-10-10

申请号：US15403311

申请日：2017-01-11

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Mujibur Rahman ,  Djordje Senicic ,  Timothy D. Anderson

IPC分类号： G06F9/30 ,  H04N19/43 ,  H04N19/513 ,  H04N19/56 ,  H04N19/433

CPC分类号： H04N19/56 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3853 ,  G06F9/3893 ,  G06F2207/5442 ,  H04N19/433 ,  H04N19/521

摘要： This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers.

公开(公告)号：US09594556B2

公开(公告)日：2017-03-14

申请号：US15074346

申请日：2016-03-18

申请人： International Business Machines Corporation

发明人： Adam J. Muff ,  Paul E. Schardt ,  Robert A. Shearer ,  Matthew R. Tubbs

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F7/00 ,  G06F7/50 ,  G06F7/483 ,  G06F7/544

CPC分类号： G06F9/3001 ,  G06F7/00 ,  G06F7/483 ,  G06F7/50 ,  G06F7/544 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3887 ,  G06F9/3895 ,  G06F2207/5442

摘要： A circuit arrangement and program product provide support for packed sum of absolute difference operations in a floating point execution unit, e.g., a scalar or vector floating point execution unit. Existing adders in a floating point execution unit may be utilized along with minimal additional logic in the floating point execution unit to support efficient execution of a fixed point packed sum of absolute differences instruction within the floating point execution unit, often eliminating the need for a separate vector fixed point execution unit in a processor architecture, and thereby leading to less logic and circuit area, lower power consumption and lower cost.

摘要翻译： 电路装置和程序产品为浮点执行单元（例如标量或向量浮点执行单元）中的绝对差分运算的压缩和提供支持。 可以利用浮点执行单元中的现有加法器以及浮点执行单元中的最小附加逻辑来支持浮点执行单元内的绝对差异指令的固定点压缩和的有效执行，通常不需要单独的 矢量定点执行单元处理器架构，从而导致逻辑和电路面积更少，功耗更低，成本更低。

公开(公告)号：US20140019713A1

公开(公告)日：2014-01-16

申请号：US13992229

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Mostafa Hagog ,  Robert Valentine ,  Amit Gradstein ,  Simon Rubanovich ,  Zeev Sperber

发明人： Elmoustapha Ould-Ahmed-Vall ,  Mostafa Hagog ,  Robert Valentine ,  Amit Gradstein ,  Simon Rubanovich ,  Zeev Sperber

IPC分类号： G06F15/78

CPC分类号： G06F9/3001 ,  G06F7/50 ,  G06F7/544 ,  G06F9/30036 ,  G06F9/3836 ,  G06F9/3877 ,  G06F15/78 ,  G06F2207/5442

摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.

摘要翻译： 用于在计算机处理器中执行的系统，装置和方法的实施例响应于包括目的地向量寄存器操作数的绝对差指令的单向量双块压缩和，绝对差（SAD）的双块压缩和，第一和第二 描述源操作数，立即数和操作码。

公开(公告)号：US08270478B2

公开(公告)日：2012-09-18

申请号：US12295457

申请日：2007-03-29

申请人： Anthony Richard Huggett

发明人： Anthony Richard Huggett

IPC分类号： H04N11/12

CPC分类号： G06F7/544 ,  G06F2207/5442 ,  H04N19/43

摘要： A logic circuit is configured to calculate a sliding sum of absolute differences of a plurality of numbers from a plurality of members respectively selected successively from all members of a sequence of numbers. The logic circuit reduces an amount of logic that is required to perform the sum of absolute differences, and thereby saves resources and latency.

摘要翻译： 逻辑电路被配置为计算从数字序列的所有成员连续选择的多个成员中的多个数字的绝对差的滑动和。 逻辑电路减少执行绝对差值之和所需的逻辑量，从而节省资源和延迟。

公开(公告)号：US20110093518A1

公开(公告)日：2011-04-21

申请号：US12581482

申请日：2009-10-19

申请人： Karthikeyan Vaithianathan ,  Arvind Sudarsanam

发明人： Karthikeyan Vaithianathan ,  Arvind Sudarsanam

IPC分类号： G06F7/50

CPC分类号： G06F7/544 ,  G06F7/505 ,  G06F7/508 ,  G06F17/10 ,  G06F2207/5442

摘要： Embodiments of a near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine are generally described herein. Other embodiments may be described and claimed. In some embodiments, a configurable two-dimensional adder tree architecture for computing a sum of absolute differences (SAD) for various block sizes up to 16 by 16 comprises a first stage of one-dimensional adder trees and a second stage of one-dimensional adder trees, wherein each one-dimensional adder tree comprises an input routing network, a plurality of adder units, and an output routing network.

摘要翻译： 这里通常描述用于任意形状的2D块绝对差（SAD）计算引擎的近似最佳可配置加法器树的实施例。 可以描述和要求保护其他实施例。 在一些实施例中，用于计算高达16×16的各种块大小的绝对差（SAD）之和的可配置二维加法器树结构包括一维加法器树的第一级和一维加法器的第二级 树，其中每个一维加法器树包括输入路由网络，多个加法器单元和输出路由网络。

公开(公告)号：US07191199B2

公开(公告)日：2007-03-13

申请号：US10640453

申请日：2003-08-13

申请人： Richard D. Simpson ,  Graeme Swanson ,  Konstantinos Venos

发明人： Richard D. Simpson ,  Graeme Swanson ,  Konstantinos Venos

IPC分类号： G06F15/00

CPC分类号： G06F7/544 ,  G06F2207/5442

摘要： Computing an absolute difference includes receiving a first value and a second value. Propagate terms are determined according to the first value and the second value at one or more adders (24). The second value is subtracted from the first value using the propagate terms to yield a subtraction difference. It is determined at one or more correctors (26) whether the subtraction difference is negative. If the subtraction difference is negative, the subtraction difference is modified according to the propagate terms to compute an absolute difference between the first value and the second value. Otherwise, the subtraction difference is reported as the absolute difference between the first value and the second value.

摘要翻译： 计算绝对差异包括接收第一值和第二值。 根据在一个或多个加法器（24）处的第一值和第二值确定传播项。 使用传播项从第一个值中减去第二个值，以产生减法差。 在一个或多个校正器（26）中确定减法差是否为负。 如果减法差为负，则根据传播项修改减法差，以计算第一值和第二值之间的绝对差。 否则，减法差被报告为第一值和第二值之间的绝对差。

公开(公告)号：US06530010B1

公开(公告)日：2003-03-04

申请号：US09475928

申请日：1999-12-30

申请人： Ching-Yu Hung ,  Leonardo W. Estevez ,  Wissam A. Rabadi

发明人： Ching-Yu Hung ,  Leonardo W. Estevez ,  Wissam A. Rabadi

IPC分类号： G06F1500

CPC分类号： G06F7/544 ,  G06F17/10 ,  G06F17/142 ,  G06F17/147 ,  G06F2207/5442 ,  H04N19/00 ,  H04N19/42 ,  H04N19/423 ,  H04N19/43 ,  H04N19/433 ,  H04N19/436 ,  H04N19/51 ,  H04N19/60

摘要： The proposed hardware architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with a downsampling (or upsampling) option, row/column Discrete Cosine Transform (DCT)/Inverse Discrete Cosine Transform (IDCT), and generic algebraic functions. The architecture is called IPP, which stands for image processing peripheral, and consists of 8 hardware multiply-accumulate units connected in parallel and routed and multiplexed together. The architecture can be dependent upon a Direct Memory Access (DMA) controller to retrieve and write back data from/to DSP memory without intervention from the DSP core. The DSP can set up the DMA transfer and IPP/DMA synchronization in advance, then go on its own processing task. Alternatively, the DSP can perform the data transfers and synchronization itself by synchronizing with the IPP architecture on these transfers. This hardware architecture implements 2-D filtering, symmetrical filtering, short filters, sum of absolute differences, and mosaic decoding more quickly(in terms of clock cycles) and efficiently than previously disclosed architectures of the prior art which perform the same operations in software.

摘要翻译： 所提出的硬件架构被集成到作为协处理器的数字信号处理器（DSP）上，以协助计算绝对差值和对数行/列有限脉冲响应（FIR）滤波与下采样（或上采样）选项，行/ 列离散余弦变换（DCT）/逆离散余弦变换（IDCT）和通用代数函数。 该架构称为IPP，代表图像处理外围设备，由并行连接并路由和复用在一起的8个硬件乘法累加单元组成。 该体系结构可以依赖于直接存储器访问（DMA）控制器来从DSP内存检索和写回数据，而不需要DSP内核的干预。 DSP可以提前设置DMA传输和IPP / DMA同步，然后进行自己的处理任务。 或者，DSP可以通过与这些传输上的IPP架构同步来执行数据传输和同步。 该硬件架构在先前公开的在软件中执行相同操作的现有技术的体系结构中实现了二维滤波，对称滤波，短滤波器，绝对差和和拼接解码的速度更快（在时钟周期方面）。

公开(公告)号：US20020062331A1

公开(公告)日：2002-05-23

申请号：US10005728

申请日：2001-11-06

发明人： Mohammad A. Abdallah ,  Vladimir Pentkovski

IPC分类号： G06F007/38

CPC分类号： G06F7/544 ,  G06F7/5332 ,  G06F7/5443 ,  G06F9/30021 ,  G06F9/30036 ,  G06F17/10 ,  G06F2207/3828 ,  G06F2207/5442

摘要： A method and apparatus that adds each one of multiple elements of a packed data together to produce a result. According to one such a method and apparatus, each of a first set of portions of partial products is produced using a first set of partial product selectors in a multiplier, each of the first set of portions of the partial products being zero. Each of the multiple elements is inserted into one of a second set of portions of the partial products using a second set of partial product selectors, each of the second set of portions of the partial products being aligned. Each of the multiple elements are added together to produce the result including a field having the sum of the multiple elements.

摘要翻译： 将打包数据的多个元素中的每一个相加在一起以产生结果的方法和装置。 根据一种这样的方法和装置，使用乘法器中的第一组部分乘积选择器来产生部分乘积的第一组部分中的每一个，部分乘积的第一组部分中的每一个为零。 使用第二组部分产品选择器将多个元件中的每一个插入到部分产品的第二组部分中的一个中，部分产品的第二组部分中的每一个对齐。 将多个元素中的每一个相加在一起以产生包括具有多个元素之和的场的结果。

公开(公告)号：US06282556B1

公开(公告)日：2001-08-28

申请号：US09451669

申请日：1999-11-30

申请人： Farzad Chehrazi ,  Vojin G. Oklobdzija

发明人： Farzad Chehrazi ,  Vojin G. Oklobdzija

IPC分类号： G06F752

CPC分类号： G06F7/5324 ,  G06F7/4991 ,  G06F7/49921 ,  G06F7/49994 ,  G06F7/5338 ,  G06F7/544 ,  G06F7/57 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30025 ,  G06F9/30145 ,  G06F2207/382 ,  G06F2207/3828 ,  G06F2207/3884 ,  G06F2207/5442

摘要： A pipelined data path architecture for use, in one embodiment, in a multimedia processor. The data path architecture requires a maximum of two execution pipestages to perform all instructions including wide data format multiply instructions and specially adapted multimedia instructions, such as the sum of absolute differences (SABD) instruction and other multiply with add (MADD) instructions. The data path architecture includes two wide data format input registers that feed four partitioned 32×32 multiplier circuits. Within two pipestages, the multiply circuit can perform one 128×128 multiply operation, four 32×32 multiply operations, eight 16×16 multiply operations or sixteen 8×8 multiply operations in parallel. The multiply circuit contains a compressor tree which generates a 256-bit sum and a 256-bit carry vector. These vectors are supplied to four 64-bit carry propagate adder circuits which generate the multiply results. When the data path architecture is performing specially adapted multimedia instructions the input registers are supplied to a pipelined logic unit containing adders, subtractors, shifters, average/round/absolute value circuits, and other logic operation circuits, compressor circuits and multiplexers. The output of the pipelined logic unit is then fed to the four 64-bit carry propagate adder circuits. In this way, the adder circuits of the multiply operation can be effectively used to also process the specially adapted multimedia instructions thereby saving IC area. Multiply circuitry is disabled to save power when the data path architecture is not processing a multiplication instruction.

摘要翻译： 在一个实施例中，在多媒体处理器中使用的流水线数据路径架构。 数据路径架构最多需要两个执行管道来执行所有指令，包括宽数据格式乘法指令和特别适应的多媒体指令，例如绝对差（SABD）指令和其他乘以加法（MADD）指令的和。 数据路径架构包括两个宽的数据格式输入寄存器，它们提供四个分区的32x32乘法器电路。 在两个管道中，乘法电路可以并行执行一个128x128乘法运算，四个32x32乘法运算，八个16x16乘法运算或十八个8x8乘法运算。 乘法电路包含一个产生256位和的256位进位向量的压缩器树。 这些矢量被提供给产生乘法结果的四个64位进位传播加法器电路。 当数据路径架构执行特别适应的多媒体指令时，输入寄存器被提供给包含加法器，减法器，移位器，平均/舍入/绝对值电路和其它逻辑运算电路，压缩器电路和多路复用器的流水线逻辑单元。 然后将流水线逻辑单元的输出馈送到四个64位进位传播加法器电路。 以这种方式，乘法运算的加法器电路可以有效地用于处理特别适应的多媒体指令，从而节省IC区域。 当数据路径架构不处理乘法指令时，禁用乘法电路以节省电力。

公开(公告)号：US5983250A

公开(公告)日：1999-11-09

申请号：US21985

申请日：1998-02-11

申请人： Teruaki Uehara

发明人： Teruaki Uehara

IPC分类号： G06F7/00 ,  G06F7/544

CPC分类号： G06F7/544 ,  G06F2207/5442

摘要： There is disclosed a compact arithmetic circuit for obtaining an absolute-valued distance (AVD) between two digital data. An inverter 11 generates the data * .beta. which is derived from the data .beta. as the 1's complement thereof. An ALU 12 adds the data .alpha. and the data * .beta. when a carry data C1 is inputted thereto. An inverter 13 generates a new carry data C2 from the add result of the ALU 12 and feeds it back to the ALU 12. Each bit of the add result by the ALU 12 is inverted by an inverter 15 and is given to a selector 14. After the initial add operation, the ALU 12 adds the data .alpha. and the data * .beta. by using carry data C2 as the input thereto. A selector 14 selects either the first add result by the ALU 12, the output data from the inverter 15 corresponding to the first add result, the second add result by the ALU 12, or the output data of the inverter 15 corresponding to the second add result, and outputs the selected as a correct AVD.

摘要翻译： 公开了一种用于获得两个数字数据之间的绝对值距离（AVD）的紧凑算术电路。 逆变器11产生从数据β导出的数据*β作为其1的互补。 当输入进位数据C1时，ALU12添加数据α和数据*β。 逆变器13根据ALU12的相加结果生成新的进位数据C2，并将其送回到ALU12。ALU12的相加结果的每一位由反相器15反相，并被送到选择器14。 在初始添加操作之后，ALU12通过使用进位数据C2作为其输入来添加数据α和数据*β。 选择器14选择ALU12的第一相加结果，来自逆变器15的与第一加法结果对应的输出数据，ALU12的第二加法结果或与第二加法相对应的反相器15的输出数据 结果，并将所选择的输出作为正确的AVD。