公开(公告)号：US08896147B2

公开(公告)日：2014-11-25

申请号：US13336503

申请日：2011-12-23

申请人： Jason J. Mangattur ,  Richard W. Fung ,  Marcus Ng

发明人： Jason J. Mangattur ,  Richard W. Fung ,  Marcus Ng

IPC分类号： H02J1/10

CPC分类号： G06F1/3287 ,  G06F1/26 ,  G06F1/3203 ,  Y02D10/171 ,  Y10T307/305 ,  Y10T307/615

摘要： A low power biasing circuit for powering up split-rail electronic circuits includes an intermediate voltage generator at each pad which is supplied by a temporary supply voltage to generate a temporary intermediate voltage only when a power signal indicates that all external voltage rails are not safe, thereby reducing power consumption.

摘要翻译： 用于对分开轨道电子电路供电的低功率偏置电路包括：在每个焊盘处的中间电压发生器，其仅在电源信号指示所有外部电压轨不安全时由临时电源电压提供以产生临时中间电压， 从而降低功耗。

公开(公告)号：US20090115457A1

公开(公告)日：2009-05-07

申请号：US12352916

申请日：2009-01-13

申请人： Junho Cho ,  Nancy Chan ,  Ramesh Senthinathan ,  Stephen Yue ,  Richard W. Fung

发明人： Junho Cho ,  Nancy Chan ,  Ramesh Senthinathan ,  Stephen Yue ,  Richard W. Fung

IPC分类号： H03K19/20

CPC分类号： H03K17/302 ,  H03K17/04106

摘要： The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.

摘要翻译： 本公开涉及一种差分信号电路，其包括具有至少一个输出和一个输入的差分信号电路，其可以在使用单个低电压电源时在多种操作模式下操作。 两个或更多个开关被包括并且被配置为根据差分信号电路的操作模式来选择性地将电源电压耦合到输出。 电路还包括可操作地耦合到至少一个开关和差分信号电路的输出的开关控制偏置电路。 开关控制偏置电路提供开关控制偏置电压，以基于输出的电压电平来控制开关的状态。 此外，体积偏置电路被包括并且可操作地耦合到开关。 体积偏置电路基于输出的电压电平选择性地向开关提供体积偏置电压。

公开(公告)号：US20130162036A1

公开(公告)日：2013-06-27

申请号：US13336481

申请日：2011-12-23

申请人： Jason J. Mangattur ,  Richard W. Fung ,  Marcus Ng

发明人： Jason J. Mangattur ,  Richard W. Fung ,  Marcus Ng

IPC分类号： H02J4/00

CPC分类号： G06F1/26 ,  Y10T307/305

摘要： A method and apparatus for powering up an integrated circuit having a plurality of power domains each coupled to receive power from one of a plurality of power sources, where each power domain includes an internal power detector which senses the power of a plurality of power domains (VDD1, VDD2, VDD3, . . . , VDDn) and compares them to a reference voltage to generate a combined power good (PG) signal. The PG signal is combined with an external system power ok signal at a plurality of AND gate circuits which are respectively powered by the plurality of power domains, thereby generating a plurality of power status signals (POWER_OK) on the destination power domains.

摘要翻译： 一种用于为具有多个功率域的集成电路供电的方法和装置，每个功率域被耦合以从多个电源之一接收功率，其中每个功率域包括检测多个功率域的功率的内部功率检测器（ VDD1，VDD2，VDD3，...，VDDn），并将其与参考电压进行比较，以产生组合功率（PG）信号。 在多个与门电路分别由多个电力域供电的PG信号与外部系统电源ok信号组合，从而在目的地电力域上产生多个电力状态信号（POWER_OK）。

公开(公告)号：US20120030488A1

公开(公告)日：2012-02-02

申请号：US12844322

申请日：2010-07-27

申请人： Richard W. Fung ,  Ricky Lau ,  Ju Tung Ng

发明人： Richard W. Fung ,  Ricky Lau ,  Ju Tung Ng

IPC分类号： G06F1/00

CPC分类号： G06F1/26 ,  G06F1/28

摘要： Methods and apparatus provide for indicating multi-power rail status of integrated circuits by taking into account a clock signal provided by, for example, core logic, in addition to considering voltage levels of multiple power rails. In one example, the apparatus includes multi-power rail status indicating logic that provides a multi-power rail status signal. The multi-power rail status signal is synchronized for assertion with a clock signal of the integrated circuit, such as the core logic of the integrated circuit, in response to an assertion of an asynchronous multi-power rail voltage stability signal. The asynchronous multi-power rail voltage stability signal indicates a state of a plurality of voltage signals from a plurality of power rails supplied to the integrated circuit. The multi-power rail status indicating logic may include a synchronous assertion/asynchronous de-assertion multi-power rail status signal generator that receives the clock signal and the asynchronous multi-power rail voltage stability signal, and in response to of the assertion of the asynchronous multi-power rail voltage stability signal, synchronizes the asynchronous multi-power rail voltage stability signal with the clock signal to assert the multi-power rail status signal.

摘要翻译： 考虑到例如核心逻辑提供的时钟信号，除了考虑多个电力轨的电​​压水平之外，方法和装置还提供用于指示集成电路的多功率轨道状态。 在一个示例中，该装置包括提供多功率轨道状态信号的多功率轨道状态指示逻辑。 响应于异步多功率轨道电压稳定信号的断言，多功率轨状态信号与集成电路的时钟信号（例如集成电路的核心逻辑）同步用于断言。 异步多功率轨电压稳定信号表示来自提供给集成电路的多个电源轨的多个电压信号的状态。 多功率轨道状态指示逻辑可以包括接收时钟信号和异步多功率轨道电压稳定性信号的同步断言/异步解除多功率轨道状态信号发生器，并且响应于断言 异步多功率轨电压稳定信号，使异步多功率轨电压稳定信号与时钟信号同步，以断言多功率轨道状态信号。

公开(公告)号：US20120025870A1

公开(公告)日：2012-02-02

申请号：US12844415

申请日：2010-07-27

申请人： Ju Tung Ng ,  Richard W. Fung ,  Ricky Lau

发明人： Ju Tung Ng ,  Richard W. Fung ,  Ricky Lau

IPC分类号： H03K19/0175

CPC分类号： H03K3/356121

摘要： Methods and apparatus provide for voltage level shifting with concurrent synchronization. The apparatus includes level shifting logic that in response to a non-level shifted clock signal from a first voltage domain, provides level shifted concurrently synchronous differential data signals in a second voltage domain based on pre-level shifted differential data signals from the first voltage domain. The first voltage domain may be, for example, a core logic voltage domain in which core logic operates. The second voltage domain may be, for example, an input/output (I/O) voltage domain in which an I/O buffer operates. The voltage level of the level shifted concurrently synchronous differential data signals is shifted from the pre-level shifted differential data signals, and the timing of the level shifted concurrently synchronous differential data signals is concurrently referenced to the non-level shifted clock signal.

摘要翻译： 方法和装置提供并行同步的电压电平转换。 该装置包括电平移位逻辑，其响应于来自第一电压域的非电平移位的时钟信号，基于来自第一电压域的预电平移位的差分数据信号在第二电压域中提供电平移动的并行同步差分数据信号 。 第一电压域可以是例如核心逻辑运行的核心逻辑电压域。 第二电压域可以是例如其中I / O缓冲器工作的输入/输出（I / O）电压域。 电平移位并行同步差分数据信号的电压电平从预电平移位的差分数据信号中移位，电平移位并行同步差分数据信号的定时同时参考非电平移位的时钟信号。

公开(公告)号：US08618866B2

公开(公告)日：2013-12-31

申请号：US10908163

申请日：2005-04-29

申请人： Richard W. Fung ,  Ramesh Senthinathan

发明人： Richard W. Fung ,  Ramesh Senthinathan

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G09G2330/02

摘要： Methods and apparatus for matching voltages between two or more circuits within an integrated circuit is disclosed. The apparatus includes a comparator circuit, comparing supply voltages to first and second circuits. The comparator outputs a variable error voltage based on the comparison, the error voltage related to the difference in voltages. The error voltage is supplied to a variable current control circuit that variably sinks one of the supply voltages to a common potential in order to increase the IR drop in the circuit supplying voltage to one of the first and second circuits, thereby affording voltage adjustment in order to match the first and second circuits. A corresponding method is also disclosed.

摘要翻译： 公开了用于在集成电路内的两个或多个电路之间匹配电压的方法和装置。 该装置包括比较器电路，用于将电源电压与第一和第二电路进行比较。 比较器根据比较输出可变误差电压，即与电压差有关的误差电压。 误差电压被提供给可变电流控制电路，其将电源电压中的一个可变地吸收到公共电位，以便将电路中的IR降低增加到第一和第二电路中的一个，从而按顺序提供电压调整 以匹配第一和第二电路。 还公开了相应的方法。

公开(公告)号：US07724037B2

公开(公告)日：2010-05-25

申请号：US12352916

申请日：2009-01-13

申请人： Junho Cho ,  Nancy Chan ,  Ramesh Senthinathan ,  Stephen Yue ,  Richard W. Fung

发明人： Junho Cho ,  Nancy Chan ,  Ramesh Senthinathan ,  Stephen Yue ,  Richard W. Fung

IPC分类号： H03K19/094

CPC分类号： H03K17/302 ,  H03K17/04106

摘要： The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.

摘要翻译： 本公开涉及一种差分信号电路，其包括具有至少一个输出和一个输入的差分信号电路，其可以在使用单个低电压电源时在多种操作模式下操作。 两个或更多个开关被包括并配置成根据差分信号电路的操作模式选择性地将电源电压耦合到输出。 电路还包括可操作地耦合到至少一个开关和差分信号电路的输出的开关控制偏置电路。 开关控制偏置电路提供开关控制偏置电压，以基于输出的电压电平来控制开关的状态。 此外，体积偏置电路被包括并且可操作地耦合到开关。 体积偏置电路基于输出的电压电平选择性地向开关提供体积偏置电压。

公开(公告)号：US07336212B2

公开(公告)日：2008-02-26

申请号：US10908197

申请日：2005-05-02

申请人： Richard W. Fung ,  Ramesh Senthinathan ,  Ronny Chan

发明人： Richard W. Fung ,  Ramesh Senthinathan ,  Ronny Chan

IPC分类号： H03M1/12 ,  G01R13/02

CPC分类号： H03M1/1225 ,  G01R19/257 ,  H03M1/56

摘要： The present disclosure relates to apparatus and methods for measurement of analog voltages in an integrated circuit. In particular, the apparatus includes an on-chip digital-to-analog converter configured to receive a variable digital input code and output a corresponding analog voltage corresponding to the variable digital input code. The apparatus also includes an on-chip comparator circuit configured to receive the analog voltage output by the digital-to-analog converter and a test analog voltage as inputs and to provide an output indicating the test analog voltage. Further, the apparatus includes an on-chip logic operative to determine the test analog voltage based on the output of the comparator circuit. A corresponding method is also disclosed.

摘要翻译： 本公开涉及用于在集成电路中测量模拟电压的装置和方法。 具体地，该装置包括片上数模转换器，其被配置为接收可变数字输入码并输出对应于可变数字输入码的相应模拟电压。 该装置还包括片上比较器电路，其被配置为接收由数模转换器输出的模拟电压和测试模拟电压作为输入，并提供指示测试模拟电压的输出。 此外，该装置包括用于基于比较器电路的输出来确定测试模拟电压的片上逻辑。 还公开了相应的方法。

公开(公告)号：US08402297B2

公开(公告)日：2013-03-19

申请号：US12844322

申请日：2010-07-27

申请人： Richard W. Fung ,  Ricky Lau ,  Ju Tung Ng

发明人： Richard W. Fung ,  Ricky Lau ,  Ju Tung Ng

IPC分类号： G06F1/28

CPC分类号： G06F1/26 ,  G06F1/28

摘要： Methods and apparatus provide for indicating multi-power rail status of integrated circuits by taking into account a clock signal provided by, for example, core logic, in addition to considering voltage levels of multiple power rails. In one example, the apparatus includes multi-power rail status indicating logic that provides a multi-power rail status signal. The multi-power rail status signal is synchronized for assertion with a clock signal of the integrated circuit, such as the core logic of the integrated circuit, in response to an assertion of an asynchronous multi-power rail voltage stability signal. The asynchronous multi-power rail voltage stability signal indicates a state of a plurality of voltage signals from a plurality of power rails supplied to the integrated circuit. The multi-power rail status indicating logic may include a synchronous assertion/asynchronous de-assertion multi-power rail status signal generator that receives the clock signal and the asynchronous multi-power rail voltage stability signal, and in response to of the assertion of the asynchronous multi-power rail voltage stability signal, synchronizes the asynchronous multi-power rail voltage stability signal with the clock signal to assert the multi-power rail status signal.

摘要翻译： 考虑到例如核心逻辑提供的时钟信号，除了考虑多个电力轨的电​​压水平之外，方法和装置还提供用于指示集成电路的多功率轨道状态。 在一个示例中，该装置包括提供多功率轨道状态信号的多功率轨道状态指示逻辑。 响应于异步多功率轨道电压稳定信号的断言，多功率轨状态信号与集成电路的时钟信号（例如集成电路的核心逻辑）同步用于断言。 异步多功率轨电压稳定信号表示来自提供给集成电路的多个电源轨的多个电压信号的状态。 多功率轨道状态指示逻辑可以包括接收时钟信号和异步多功率轨道电压稳定性信号的同步断言/异步解除多功率轨道状态信号发生器，并且响应于断言 异步多功率轨电压稳定信号，使异步多功率轨电压稳定信号与时钟信号同步，以断言多功率轨道状态信号。

公开(公告)号：US07495477B2

公开(公告)日：2009-02-24

申请号：US11830897

申请日：2007-07-31

申请人： Junho Cho ,  Nancy Chan ,  Ramesh Senthinathan ,  Stephen Yue ,  Richard W. Fung

发明人： Junho Cho ,  Nancy Chan ,  Ramesh Senthinathan ,  Stephen Yue ,  Richard W. Fung

IPC分类号： H03K19/094

CPC分类号： H03K17/302 ,  H03K17/04106

摘要： The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.

摘要翻译： 本公开涉及一种差分信号电路，其包括具有至少一个输出和一个输入的差分信号电路，其可以在使用单个低电压电源时在多种操作模式下操作。 两个或更多个开关被包括并配置成根据差分信号电路的操作模式选择性地将电源电压耦合到输出。 电路还包括可操作地耦合到开关中的至少一个和差分信号电路的输出的开关控制偏置电路。 开关控制偏置电路提供开关控制偏置电压，以基于输出的电压电平来控制开关的状态。 此外，体积偏置电路被包括并且可操作地耦合到开关。 体积偏置电路基于输出的电压电平选择性地向开关提供体积偏置电压。