公开(公告)号：US08286022B2

公开(公告)日：2012-10-09

申请号：US12352114

申请日：2009-01-12

申请人： Richard Fung ,  Ramesh Senthinathan ,  Nancy Chan

发明人： Richard Fung ,  Ramesh Senthinathan ,  Nancy Chan

IPC分类号： G06F1/12

CPC分类号： H03K5/151 ,  G06F1/10 ,  H04L25/0272 ,  H04L25/03878

摘要： A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with deterministic skew adjustment set during a receiver training period. Intrapair skew refers to the skew within a pair of differential signals, and is hence interchangeable with the term differential skew in the context of this document. During the receiver training period, a training data pattern is received, such as alternating ones and zeros (e.g., a D10.2 pattern as is known in the art), rather than an actual data payload. The differential serial communication receiver circuit includes a differential skew compensation circuit to compensate for intrapair skew. The differential skew compensation circuit receives a pair of complementary differential input signals including a noninverting input signal and an inverting input signal, and in response generates a skew compensated first differential output signal and a skew compensated second differential output signal. The differential skew compensation circuit compares the relative delay of the skew compensated first differential output signal and the skew compensated second differential output signal, and in response delays at least one of the noninverting input signal or the inverting input signal to reduce intrapair skew.

摘要翻译： 差分串行通信接收器电路自动补偿串行差分通信链路上接收到的差分信号之间的时间间隔偏移，并在接收机训练期间设置确定性偏移调整。 内部偏斜是指一对差分信号内的偏斜，因此可以与本文档上下文中的术语差分偏移互换。 在接收机训练期间，接收训练数据模式，例如交替的零和零（例如本领域已知的D10.2模式），而不是实际的数据有效载荷。 差分串行通信接收器电路包括差分偏移补偿电路，以补偿内部偏移。 差分偏移补偿电路接收包括非反相输入信号和反相输入信号的一对互补差分输入信号，并且响应于产生偏斜补偿的第一差分输出信号和偏斜补偿的第二差分输出信号。 差分偏移补偿电路比较偏斜补偿的第一差分输出信号和偏斜补偿的第二差分输出信号的相对延迟，并且响应延迟至少一个同相输入信号或反相输入信号，以减少行间偏斜。

公开(公告)号：US20110050314A1

公开(公告)日：2011-03-03

申请号：US12862298

申请日：2010-08-24

申请人： David I.J. Glen ,  Collis Quinn Carter ,  Natan Shtutman ,  Ngar Sze Nancy Chan ,  Michael Foxcroft

发明人： David I.J. Glen ,  Collis Quinn Carter ,  Natan Shtutman ,  Ngar Sze Nancy Chan ,  Michael Foxcroft

IPC分类号： G06F1/04

CPC分类号： G06F1/06 ,  G09G5/006

摘要： An apparatus includes a clock circuit and a plurality of display interface circuits. The clock circuit provides a common clock signal. The display interface circuits each provide a respective display link clock signal in response to the common clock signal. One of the display link clock signals is at a different clock speed that another of the display link clock signals.

摘要翻译： 一种装置包括时钟电路和多个显示接口电路。 时钟电路提供公共时钟信号。 显示接口电路各自响应公共时钟信号提供相应的显示链路时钟信号。 其中一个显示链路时钟信号处于与另一个显示链路时钟信号不同的时钟速度。

公开(公告)号：US20070120583A1

公开(公告)日：2007-05-31

申请号：US11164622

申请日：2005-11-30

申请人： Shirley Lam ,  Nancy Chan ,  Mikhail Rodionov ,  Ramesh Senthinathan

发明人： Shirley Lam ,  Nancy Chan ,  Mikhail Rodionov ,  Ramesh Senthinathan

IPC分类号： H03L7/06

CPC分类号： H03L7/0802 ,  H03L7/0891 ,  H03L7/10

摘要： In a method and apparatus for using a clock generating circuit to minimize settling time after dynamic power supply voltage ramping, a clock signal may be generated using a clock generating circuit having, among other things, open feedback loop switch logic and a dynamic fast lock control signal generator. Whereupon, when in operation, the open feedback loop switch logic is responsive to a controlled change in power supply voltage condition such that a feedback loop of the clock generating circuit is opened during power supply voltage ramping (e.g., during transitions to or from battery conservation modes). In response to opening the feedback loop, the dynamic fast lock control signal generator selectively applies a stabilizing control signal to a variable clock signal generator (e.g., a voltage controlled oscillator) such that the generated clock signal can quickly lock onto the proper target frequency.

摘要翻译： 在使用时钟发生电路来最小化动态电源电压斜坡上的建立时间的方法和装置中，可以使用具有开放反馈回路开关逻辑和动态快速锁定控制的时钟产生电路来产生时钟信号 信号发生器。 于是，在运行时，开路反馈环路开关逻辑响应电源电压条件的受控变化，使得时钟发生电路的反馈回路在电源电压斜坡期间打开（例如，在转换到电池保护期间 模式）。 响应于打开反馈回路，动态快速锁定控制信号发生器选择性地将稳定控制信号施加到可变时钟信号发生器（例如，压控振荡器），使得所产生的时钟信号可以快速锁定到适当的目标频率上。

公开(公告)号：US20060123177A1

公开(公告)日：2006-06-08

申请号：US11004201

申请日：2004-12-02

申请人： Nancy Chan ,  Ramesh Senthinathan

发明人： Nancy Chan ,  Ramesh Senthinathan

IPC分类号： G06F13/42

CPC分类号： H03L7/06 ,  H04L7/0008 ,  H04L25/0272 ,  H04L25/0276

摘要： A differential serial communication transmitter (i.e. PCI Express or other suitable type of transmitter) can be used to transport and interoperate transition minimized differential signaling. The differential serial communication transmitter control logic receives display configuration control data and in response configures at least one differential serial communication transmitter of a plurality of differential serial communication transmitters in an integrated circuit for communication with a display (i.e. visual digital display) employing transition minimized differential signaling. For example, the integrated circuit, such as a graphics processor, may include the plurality of differential serial communication transmitters for communication with devices, such as a northbridge circuit and a display within a computer system. The differential serial communication transmitter control logic may configure at least one of the plurality of differential serial communication transmitters for communication with the display via a differential serial communication display link (i.e. DVI or other suitable type of link). The plurality of differential serial communication transmitters may also be configured for communication with one or more other devices, such as with a bridge circuit such as a northbridge.

摘要翻译： 可以使用差分串行通信发射机（即PCI Express或其他合适类型的发射机）来传输和互操作转换最小化的差分信令。 差分串行通信发射机控制逻辑接收显示配置控制数据，并且作为响应，在集成电路中配置多个差分串行通信发射机的至少一个差分串行通信发射机，用于与使用转换最小化差分的显示器（即可视数字显示器）进行通信 信令。 例如，诸如图形处理器的集成电路可以包括用于与设备（例如北桥电路和计算机系统内的显示器）通信的多个差分串行通信发射器。 差分串行通信发射机控制逻辑可以配置多个差分串行通信发射机中的至少一个，用于经由差分串行通信显示链路（即，DVI或其他合适类型的链路）与显示器进行通信。 多个差分串行通信发射机还可以被配置为与一个或多个其他设备进行通信，例如用诸如北桥的桥接电路进行通信。

公开(公告)号：US09348355B2

公开(公告)日：2016-05-24

申请号：US12862298

申请日：2010-08-24

申请人： David I. J. Glen ,  Collis Quinn Carter ,  Natan Shtutman ,  Ngar Sze Nancy Chan ,  Michael Foxcroft

发明人： David I. J. Glen ,  Collis Quinn Carter ,  Natan Shtutman ,  Ngar Sze Nancy Chan ,  Michael Foxcroft

IPC分类号： G09G5/00 ,  G06F1/06

CPC分类号： G06F1/06 ,  G09G5/006

摘要： An apparatus includes a clock circuit and a plurality of display interface circuits. The clock circuit provides a common clock signal. The display interface circuits each provide a respective display link clock signal in response to the common clock signal. One of the display link clock signals is at a different clock speed that another of the display link clock signals.

摘要翻译： 一种装置包括时钟电路和多个显示接口电路。 时钟电路提供公共时钟信号。 显示接口电路各自响应公共时钟信号提供相应的显示链路时钟信号。 其中一个显示链路时钟信号处于与另一个显示链路时钟信号不同的时钟速度。

公开(公告)号：US08330476B2

公开(公告)日：2012-12-11

申请号：US11215918

申请日：2005-08-31

申请人： Nancy Chan ,  Ramesh Senthinathan

发明人： Nancy Chan ,  Ramesh Senthinathan

IPC分类号： G01R27/08

CPC分类号： H01L23/34 ,  G06F1/26 ,  G06F11/3024 ,  G06F11/3051 ,  G06F11/3058 ,  H01L2924/0002 ,  H01L2924/00

摘要： A supply voltage management system and method for an integrated circuit (IC) die are provided. The supply voltage management system includes one or more temperature sensing elements located on the IC die and configured to sense temperature of the die and to output a sensed temperature value for the die. A dynamic voltage controller is located on the die and is configured to receive the sensed temperature value for the die and to identify a technology process category of the die. Based on the sensed temperature value and the identified technology process category of the die, the dynamic voltage controller adjusts an output voltage to at least one circuit of the die.

摘要翻译： 提供了一种用于集成电路（IC）管芯的电源电压管理系统和方法。 电源电压管理系统包括位于IC管芯上的​​一个或多个温度检测元件，其配置为感测管芯的温度并输出检测到的管芯温度值。 动态电压控制器位于管芯上并且被配置为接收针对管芯的感测温度值并且识别管芯的技术工艺类别。 基于感测的温度值和所识别的管芯工艺过程类别，动态电压控制器调节至少一个管芯电路的输出电压。

公开(公告)号：US20110066778A1

公开(公告)日：2011-03-17

申请号：US12944495

申请日：2010-11-11

申请人： Nancy Chan ,  Ramesh Senthinathan

发明人： Nancy Chan ,  Ramesh Senthinathan

IPC分类号： G06F13/42

CPC分类号： H03L7/06 ,  H04L7/0008 ,  H04L25/0272 ,  H04L25/0276

摘要： A differential serial communication transmitter (i.e. PCI Express or other suitable type of transmitter) can be used to transport and interoperate transition minimized differential signaling. The differential serial communication transmitter control logic receives display configuration control data and in response configures at least one differential serial communication transmitter of a plurality of differential serial communication transmitters in an integrated circuit for communication with a display (i.e. visual digital display) employing transition minimized differential signaling. For example, the integrated circuit, such as a graphics processor, may include the plurality of differential serial communication transmitters for communication with devices, such as a northbridge circuit and a display within a computer system. The differential serial communication transmitter control logic may configure at least one of the plurality of differential serial communication transmitters for communication with the display via a differential serial communication display link (i.e. DVI or other suitable type of link). The plurality of differential serial communication transmitters may also be configured for communication with one or more other devices, such as with a bridge circuit such as a northbridge.

摘要翻译： 可以使用差分串行通信发射机（即PCI Express或其他合适类型的发射机）来传输和互操作转换最小化的差分信令。 差分串行通信发射机控制逻辑接收显示配置控制数据，并且作为响应，在集成电路中配置多个差分串行通信发射机的至少一个差分串行通信发射机，用于与使用转换最小化差分的显示器（即可视数字显示器）进行通信 信令。 例如，诸如图形处理器的集成电路可以包括用于与设备（例如北桥电路和计算机系统内的显示器）通信的多个差分串行通信发射器。 差分串行通信发射机控制逻辑可以配置多个差分串行通信发射机中的至少一个，用于经由差分串行通信显示链路（即，DVI或其他合适类型的链路）与显示器进行通信。 多个差分串行通信发射机还可以被配置为与一个或多个其他设备进行通信，例如用诸如北桥的桥接电路进行通信。

公开(公告)号：US07493509B2

公开(公告)日：2009-02-17

申请号：US11010159

申请日：2004-12-10

申请人： Richard Fung ,  Ramesh Senthinathan ,  Nancy Chan

发明人： Richard Fung ,  Ramesh Senthinathan ,  Nancy Chan

IPC分类号： G06F1/12

CPC分类号： H03K5/151 ,  G06F1/10 ,  H04L25/0272 ,  H04L25/03878

摘要： A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with deterministic skew adjustment set during a receiver training period. Intrapair skew refers to the skew within a pair of differential signals, and is hence interchangeable with the term differential skew in the context of this document. During the receiver training period, a training data pattern is received, such as alternating ones and zeros (e.g., a D10.2 pattern as is known in the art), rather than an actual data payload. The differential serial communication receiver circuit includes a differential skew compensation circuit to compensate for intrapair skew. The differential skew compensation circuit receives a pair of complementary differential input signals including a noninverting input signal and an inverting input signal, and in response generates a skew compensated first differential output signal and a skew compensated second differential output signal. The differential skew compensation circuit compares the relative delay of the skew compensated first differential output signal and the skew compensated second differential output signal, and in response delays at least one of the noninverting input signal or the inverting input signal to reduce intrapair skew.

摘要翻译： 差分串行通信接收器电路自动补偿串行差分通信链路上接收到的差分信号之间的时间间隔偏移，并在接收机训练期间设置确定性偏移调整。 内部偏斜是指一对差分信号内的偏斜，因此可以与本文档上下文中的术语差分偏移互换。 在接收机训练期间，接收训练数据模式，例如交替的零和零（例如本领域已知的D10.2模式），而不是实际的数据有效载荷。 差分串行通信接收器电路包括差分偏移补偿电路，以补偿内部偏移。 差分偏移补偿电路接收包括非反相输入信号和反相输入信号的一对互补差分输入信号，并且响应于产生偏斜补偿的第一差分输出信号和偏斜补偿的第二差分输出信号。 差分偏移补偿电路比较偏斜补偿的第一差分输出信号和偏斜补偿的第二差分输出信号的相对延迟，并且响应延迟至少一个同相输入信号或反相输入信号，以减少行间偏斜。

公开(公告)号：US20070268043A1

公开(公告)日：2007-11-22

申请号：US11830897

申请日：2007-07-31

申请人： Junho Cho ,  Nancy Chan ,  Ramesh Senthinathan ,  Stephen Yue ,  Richard Fung

发明人： Junho Cho ,  Nancy Chan ,  Ramesh Senthinathan ,  Stephen Yue ,  Richard Fung

IPC分类号： H03K19/20 ,  H03K19/094

CPC分类号： H03K17/302 ,  H03K17/04106

摘要： The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.

摘要翻译： 本公开涉及一种差分信号电路，其包括具有至少一个输出和一个输入的差分信号电路，其可以在使用单个低电压电源时在多种操作模式下操作。 两个或更多个开关被包括并配置成根据差分信号电路的操作模式选择性地将电源电压耦合到输出。 电路还包括可操作地耦合到至少一个开关和差分信号电路的输出的开关控制偏置电路。 开关控制偏置电路提供开关控制偏置电压，以基于输出的电压电平来控制开关的状态。 此外，体积偏置电路被包括并且可操作地耦合到开关。 体积偏置电路基于输出的电压电平选择性地向开关提供体积偏置电压。

公开(公告)号：US20070152734A1

公开(公告)日：2007-07-05

申请号：US11306475

申请日：2005-12-29

申请人： Ramesh Senthinathan ,  Nancy Chan

发明人： Ramesh Senthinathan ,  Nancy Chan

IPC分类号： G11C5/14

CPC分类号： G11C29/02 ,  G11C5/147 ,  G11C29/021 ,  G11C29/028

摘要： In a method and apparatus for generating a power supply voltage, an integrated circuit including an adaptive power supply voltage circuit is provided where a target signal is generated representing an ideal or approximated ideal performance characteristic of a functional block operating with the power supply voltage. A generated functional block test signal is generated representing the performance characteristic of the functional block under these conditions. The adaptive power supply voltage circuit compares the target signal with the generated functional block test signal and adjusts the power supply voltage continuously until the target signal and generated functional block test signal are substantially equal. When the target signal and generated functional block test signal are substantially equal, the power supply voltage is locked for subsequent use. By optimizing the power supply voltage, minimal power dissipation is provided.

摘要翻译： 在用于产生电源电压的方法和装置中，提供了包括自适应电源电压电路的集成电路，其中产生的目标信号表示用电源电压工作的功能块的理想或近似的理想性能特性。 生成的功能块测试信号在这些条件下表示功能块的性能特征。 自适应电源电压电路将目标信号与产生的功能块测试信号进行比较，并连续调整电源电压，直到目标信号和产生的功能块测试信号基本相等。 当目标信号和产生的功能块测试信号基本相等时，电源电压被锁定以供后续使用。 通过优化电源电压，提供最小的功耗。