公开(公告)号：US20070098111A1

公开(公告)日：2007-05-03

申请号：US11261166

申请日：2005-10-27

申请人： Mark Gehring ,  Russell Moen ,  Brent Jensen

发明人： Mark Gehring ,  Russell Moen ,  Brent Jensen

IPC分类号： H04L27/12

CPC分类号： H04L27/2092

摘要： A transmitter digital signal processor (DSP) circuit has a transmit frequency represented by n-bit data output from a look up table (LUT). The n-bit data is outputted to an n-bit accumulator structured to overflow at a rate based on the output n-bit data to output a phase. The circuit further has device structured to add an n-bit signed constant to the accumulator to offset the frequency represented by the n-bit data output from the LUT. A transceiver on a semiconductor chip may include as part of a transmitter circuit, a transmit DSP circuit that has the LUT, accumulator and device providing an n-bit signed constant to the accumulator to offset a transmit frequency in order to allow a receiver circuit on the transceiver to communicate directly with the transmitter circuit, and thus allowing testing of the transceiver.

摘要翻译： 发射机数字信号处理器（DSP）电路具有由查找表（LUT）输出的n位数据表示的发射频率。 n比特数据被输出到构成为以基于输出n比特数据的速率溢出的n比特累加器，以输出相位。 电路还具有被构造为向累加器添加n位有符号常数以便偏移由LUT输出的n位数据表示的频率的器件。 半导体芯片上的收发器可以包括作为发射机电路的一部分的发射DSP电路，其具有LUT，累加器和设备向累加器提供n位有符号常数以偏移发射频率，以允许接收机电路 收发器与发射机电路直接通信，从而允许对收发器进行测试。

公开(公告)号：US20070004370A1

公开(公告)日：2007-01-04

申请号：US11427712

申请日：2006-06-29

申请人： MARK GEHRING ,  RUSSELL MOEN

发明人： MARK GEHRING ,  RUSSELL MOEN

IPC分类号： H04B1/26

CPC分类号： H04B1/28

摘要： A method of communication between a first transceiver having a first local oscillator set at a first frequency and a second transceiver having a second local oscillator set at a second frequency disclosed. The method includes transmitting a first signal at a first frequency from the first transceiver to the second transceiver, transmitting a second signal at the second frequency from the second transceiver to the first transceiver, and receiving the second signal at the first transceiver. The method further includes maintaining the first local oscillator at the first frequency and the second local oscillator at the second frequency during the transmitting of the first signal, during the receiving of the first signal, during the transmitting of the second signal, and during the receiving of the second signal.

摘要翻译： 一种在具有以第一频率设置的第一本地振荡器的第一收发器和第二收发器之间的通信方法，所述第二收发器具有以公开的第二频率设置的第二本地振荡器。 该方法包括以第一频率从第一收发机向第二收发信机发射第一信号，以第二频率将第二信号从第二收发信机发射到第一收发信机，以及在第一收发信机接收第二信号。 该方法还包括在发送第一信号期间，在接收第一信号期间，在发送第二信号期间以及在接收期间，将第一本地振荡器保持在第一频率处的第一本地振荡器和第二本地振荡器处于第二频率 的第二信号。

公开(公告)号：US06744323B1

公开(公告)日：2004-06-01

申请号：US09943149

申请日：2001-08-30

申请人： Nathan Y. Moyal ,  Mark R. Gehring ,  Russell Moen ,  Lawrence Ragan

发明人： Nathan Y. Moyal ,  Mark R. Gehring ,  Russell Moen ,  Lawrence Ragan

IPC分类号： H03L700

CPC分类号： H03L7/10 ,  H03L7/095 ,  H03L7/18 ,  Y10S331/02

摘要： An apparatus comprising a phase lock loop (PLL) and a lock circuit. The PLL may be configured to multiply an input frequency in response to a lock signal. The lock circuit may be configured to generate the lock signal. The PLL may also be configured to select a reference frequency as (i) the input frequency when in a first mode and (ii) a divided frequency of the input frequency when in a second mode.

摘要翻译： 一种包括锁相环（PLL）和锁电路的装置。 PLL可以被配置为响应于锁定信号来乘以输入频率。 锁定电路可以被配置为产生锁定信号。 PLL还可以被配置为在第一模式中选择参考频率为（i）输入频率，以及（ii）当处于第二模式时输入频率的分频。