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    TRI-STATING A PHASE LOCKED LOOP TO CONSERVE POWER
    1.
    发明申请
    TRI-STATING A PHASE LOCKED LOOP TO CONSERVE POWER 有权
    三相锁定环路以保持功率

    公开(公告)号：US20070082635A1

    公开(公告)日：2007-04-12

    申请号：US11467346

    申请日：2006-08-25

    申请人： Mark Gehring ,  Nathan Moyal

    发明人： Mark Gehring ,  Nathan Moyal

    IPC分类号： H04B1/18 ,  H04B7/00 ,  H04B1/06

    CPC分类号： H03L7/0802 ,  H03L7/0891 ,  H03L7/14 ,  H03L7/18

    摘要： In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a design frequency. After the capacitor is stabilized, power to some of the components in the PLL is reduced.

    摘要翻译： 在具有间歇操作无线电的系统中，其频率由锁相环（PLL）控制，一种用于通过在PLL之后对PLL中的控制电容器进行三态化来降低PLL消耗的功率的方法和系统 稳定在设计频率。 电容器稳定后，PLL中某些组件的电源减少。

    RF power amplifier controller circuit including calibrated phase control loop
    2.
    发明授权
    RF power amplifier controller circuit including calibrated phase control loop 有权
    RF功率放大器控制器电路包括校准相位控制回路

    公开(公告)号：US07917106B2

    公开(公告)日：2011-03-29

    申请号：US11669648

    申请日：2007-01-31

    申请人： Serge Francois Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Cary Renzema ,  Jeremy Lubkin

    发明人： Serge Francois Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Cary Renzema ,  Jeremy Lubkin

    IPC分类号： H04B1/04 ,  H03G3/20

    CPC分类号： H03F1/0205 ,  H03F1/0227 ,  H03F1/0238 ,  H03F1/3247 ,  H03F3/24 ,  H03F2200/451 ,  H03F2200/78 ,  H03F2200/99 ,  H03G3/004 ,  H03G3/3042 ,  H04B2001/0408

    摘要： An RF power amplifier system comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal. The phase control loop may comprise one or more variable phase delays introducing a relative phase delay to allow the phase differences between the input and output signals of the PA circuit to be within a range compatible with a phase comparator generating the phase error signal, and a low frequency blocking module that removes the larger extent, lower frequency components of the phase error signal.

    摘要翻译： RF功率放大器系统包括幅度控制环路和相位控制环路。 幅度控制环路基于表示输入信号的振幅与输出信号的衰减幅度之间的振幅差的振幅校正信号，调整功率放大器的电源电压。 相位控制环路基于表示输入信号的相位与输出信号的相位差的相位误差信号来调整输入信号的相位。 相位控制回路可以包括引入相对相位延迟的一个或多个可变相位延迟，以允许PA电路的输入和输出信号之间的相位差在与产生相位误差信号的相位比较器兼容的范围内，以及 低频阻塞模块可以消除较大的程度，降低频率分量的相位误差信号。

    RF power amplifier controller circuit including calibrated phase control loop
    3.
    发明授权
    RF power amplifier controller circuit including calibrated phase control loop 有权
    RF功率放大器控制器电路包括校准相位控制回路

    公开(公告)号：US08340604B2

    公开(公告)日：2012-12-25

    申请号：US13034587

    申请日：2011-02-24

    申请人： Serge Francois Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Cary Renzema ,  Jeremy Lubkin

    发明人： Serge Francois Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Cary Renzema ,  Jeremy Lubkin

    IPC分类号： H04B1/16

    CPC分类号： H03F1/0205 ,  H03F1/0227 ,  H03F1/0238 ,  H03F1/3247 ,  H03F3/24 ,  H03F2200/451 ,  H03F2200/78 ,  H03F2200/99 ,  H03G3/004 ,  H03G3/3042 ,  H04B2001/0408

    摘要： An RF power amplifier system comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal. The phase control loop may comprise one or more variable phase delays introducing a relative phase delay to allow the phase differences between the input and output signals of the PA circuit to be within a range compatible with a phase comparator generating the phase error signal, and a low frequency blocking module that removes the larger extent, lower frequency components of the phase error signal.

    摘要翻译： RF功率放大器系统包括幅度控制环路和相位控制环路。 幅度控制环路基于表示输入信号的振幅与输出信号的衰减幅度之间的振幅差的振幅校正信号，调整功率放大器的电源电压。 相位控制环路基于表示输入信号的相位与输出信号的相位差的相位误差信号来调整输入信号的相位。 相位控制回路可以包括引入相对相位延迟的一个或多个可变相位延迟，以允许PA电路的输入和输出信号之间的相位差在与产生相位误差信号的相位比较器兼容的范围内，以及 低频阻塞模块可以消除较大的程度，降低频率分量的相位误差信号。

    RF Power Amplifier Controller Circuit Including Calibrated Phase Control Loop
    4.
    发明申请
    RF Power Amplifier Controller Circuit Including Calibrated Phase Control Loop 有权
    包括校准相位控制回路的RF功率放大器控制器电路

    公开(公告)号：US20110140777A1

    公开(公告)日：2011-06-16

    申请号：US13034587

    申请日：2011-02-24

    申请人： Serge Francois Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Cary Renzema ,  Jeremy Lubkin

    发明人： Serge Francois Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Cary Renzema ,  Jeremy Lubkin

    IPC分类号： H03G3/20

    CPC分类号： H03F1/0205 ,  H03F1/0227 ,  H03F1/0238 ,  H03F1/3247 ,  H03F3/24 ,  H03F2200/451 ,  H03F2200/78 ,  H03F2200/99 ,  H03G3/004 ,  H03G3/3042 ,  H04B2001/0408

    摘要： An RF power amplifier system comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal. The phase control loop may comprise one or more variable phase delays introducing a relative phase delay to allow the phase differences between the input and output signals of the PA circuit to be within a range compatible with a phase comparator generating the phase error signal, and a low frequency blocking module that removes the larger extent, lower frequency components of the phase error signal.

    摘要翻译： RF功率放大器系统包括幅度控制环路和相位控制环路。 幅度控制环路基于表示输入信号的振幅与输出信号的衰减幅度之间的振幅差的振幅校正信号，调整功率放大器的电源电压。 相位控制环路基于表示输入信号的相位与输出信号的相位差的相位误差信号来调整输入信号的相位。 相位控制回路可以包括引入相对相位延迟的一个或多个可变相位延迟，以允许PA电路的输入和输出信号之间的相位差在与产生相位误差信号的相位比较器兼容的范围内，以及 低频阻塞模块可以消除较大的程度，降低频率分量的相位误差信号。

    RF Power Amplifier Controller Circuit Including Calibrated Phase Control Loop
    5.
    发明申请
    RF Power Amplifier Controller Circuit Including Calibrated Phase Control Loop 有权
    包括校准相位控制回路的RF功率放大器控制器电路

    公开(公告)号：US20070184794A1

    公开(公告)日：2007-08-09

    申请号：US11669648

    申请日：2007-01-31

    申请人： Serge Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Cary Renzema ,  Jeremy Lubkin

    发明人： Serge Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Cary Renzema ,  Jeremy Lubkin

    IPC分类号： H04B1/04 ,  H01Q11/12

    CPC分类号： H03F1/0205 ,  H03F1/0227 ,  H03F1/0238 ,  H03F1/3247 ,  H03F3/24 ,  H03F2200/451 ,  H03F2200/78 ,  H03F2200/99 ,  H03G3/004 ,  H03G3/3042 ,  H04B2001/0408

    摘要： An RF power amplifier system comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal. The phase control loop may comprise one or more variable phase delays introducing a relative phase delay to allow the phase differences between the input and output signals of the PA circuit to be within a range compatible with a phase comparator generating the phase error signal, and a low frequency blocking module that removes the larger extent, lower frequency components of the phase error signal.

    摘要翻译： RF功率放大器系统包括幅度控制环路和相位控制环路。 幅度控制环路基于表示输入信号的振幅与输出信号的衰减幅度之间的振幅差的振幅校正信号，调整功率放大器的电源电压。 相位控制环路基于表示输入信号的相位与输出信号的相位差的相位误差信号来调整输入信号的相位。 相位控制回路可以包括引入相对相位延迟的一个或多个可变相位延迟，以允许PA电路的输入和输出信号之间的相位差在与产生相位误差信号的相位比较器兼容的范围内，以及 低频阻塞模块可以消除较大的程度，降低频率分量的相位误差信号。

    REDUCING THE SETTLING TIME OF A CRYSTAL OSCILLATOR
    6.
    发明申请
    REDUCING THE SETTLING TIME OF A CRYSTAL OSCILLATOR 有权
    降低晶体振荡器的稳定时间

    公开(公告)号：US20070069829A1

    公开(公告)日：2007-03-29

    申请号：US11465439

    申请日：2006-08-17

    申请人： MARK GEHRING

    发明人： MARK GEHRING

    IPC分类号： H03B5/32

    CPC分类号： H03B5/32 ,  H03B5/06 ,  H03B2200/0094 ,  H03L7/00

    摘要： A method and system for initiating the oscillation of a crystal that controls a crystal oscillator by applying an initiating pulse to said crystal. The initiating pulse having a pulse width less than one half the periodicity of said crystal.

    摘要翻译： 一种用于通过向所述晶体施加起始脉冲来启动控制晶体振荡器的晶体的振荡的方法和系统。 该起始脉冲的脉冲宽度小于所述晶体周期的一半。

    CIRCUIT FOR CREATING TRACKING TRANSCONDUCTORS OF DIFFERENT TYPES
    7.
    发明申请
    CIRCUIT FOR CREATING TRACKING TRANSCONDUCTORS OF DIFFERENT TYPES 有权
    用于创建不同类型的跟踪传感器的电路

    公开(公告)号：US20070046368A1

    公开(公告)日：2007-03-01

    申请号：US11467067

    申请日：2006-08-24

    申请人： Mark Gehring ,  Joseph Stenger

    发明人： Mark Gehring ,  Joseph Stenger

    IPC分类号： H03F3/191

    CPC分类号： H03F3/191 ,  H03F3/45475 ,  H03F2200/453 ,  H03F2203/45288

    摘要： Systems and method for tracking different types of transconductance cells is shown and described. In these multi-cell systems, the addition of one or more tracking control modules allows circuit designers to advantageously incorporate multiple transconductor topologies and their uniquely beneficial characteristics into their designs, without eradicating its centralized multi-cell tuning functionality.

    摘要翻译： 示出并描述了用于跟踪不同类型的跨导单元的系统和方法。 在这些多单元系统中，添加一个或多个跟踪控制模块允许电路设计者有利地将多个跨导体拓扑及其独特的有益特征结合到其设计中，而无需消除其集中的多单元调谐功能。

    Phase locked loop operable over a wide frequency range
    8.
    发明授权
    Phase locked loop operable over a wide frequency range 有权
    锁相环在宽频率范围内可操作

    公开(公告)号：US07109763B1

    公开(公告)日：2006-09-19

    申请号：US10796873

    申请日：2004-03-08

    申请人： Nathan Moyal ,  Eric Mitchell ,  Mark Gehring

    发明人： Nathan Moyal ,  Eric Mitchell ,  Mark Gehring

    IPC分类号： H03L7/00

    CPC分类号： H03L7/183 ,  H03L7/099 ,  H03L7/10 ,  H03L2207/06

    摘要： A Phase Locked Loop (PLL) that has a substantially constant gain over a wide frequency range. The frequency range over which the PLL operates is divided into a number of frequency sub-ranges. The circuit includes a mechanism for adjusting the loop gain profile as the PLL moves from one frequency sub-range to another. When the PLL switches to a new frequency sub-range, the loop gain profile is adjusted to a pre-established value. Changes of frequency within each sub-range are then accomplished with the loop gain varying within a pre-established range.

    摘要翻译： 锁相环（PLL），其在宽频率范围内具有基本恒定的增益。 PLL操作的频率范围被分为多个频率子范围。 该电路包括当PLL从一个频率子范围移动到另一个频率子范围时调整环路增益曲线的机构。 当PLL切换到新的频率子范围时，环路增益曲线调整到预先建立的值。 然后，在每个子范围内的频率变化，其中环路增益在预先建立的范围内变化。

    Circuit and method for improving frequency range in a phase locked loop
    9.
    发明授权
    Circuit and method for improving frequency range in a phase locked loop 有权
    提高锁相环频率范围的电路及方法

    公开(公告)号：US07432749B1

    公开(公告)日：2008-10-07

    申请号：US10875667

    申请日：2004-06-23

    申请人： Mark Gehring ,  Nathan Moyal

    发明人： Mark Gehring ,  Nathan Moyal

    IPC分类号： H03L7/06

    CPC分类号： H03L7/10 ,  H03L7/0891 ,  H03L7/18

    摘要： A circuit and method for providing a periodic clock signal, such as a high frequency clock signal. In one example, the circuit may include a phase locked loop circuit having a voltage controlled oscillator, the voltage controlled oscillator having a voltage input, a calibration input, and a clock signal output; and a logic circuit for dynamically calibrating an operating frequency of the phase locked loop during operation of the phase locked loop. In one embodiment, the logic circuit may compare an input voltage into the voltage controlled oscillator against a reference voltage, and if the input voltage is lower than the reference voltage, the logic circuit decreases the operating frequency of the phase locked loop circuit. The logic circuit may compare an input voltage into the voltage controlled oscillator against a reference voltage, and if the input voltage is higher than the reference voltage, the logic circuit increases the operating frequency of the phase locked loop circuit.

    摘要翻译： 一种用于提供诸如高频时钟信号的周期性时钟信号的电路和方法。 在一个示例中，电路可以包括具有压控振荡器的锁相环电路，压控振荡器具有电压输入，校准输入和时钟信号输出; 以及用于在锁相环操作期间动态地校准锁相环的工作频率的逻辑电路。 在一个实施例中，逻辑电路可以将参考电压中的压控振荡器的输入电压进行比较，如果输入电压低于参考电压，则逻辑电路降低锁相环电路的工作频率。 逻辑电路可以将压控振荡器的输入电压与参考电压进行比较，如果输入电压高于参考电压，则逻辑电路增加了锁相环电路的工作频率。