公开(公告)号：US08476142B2

公开(公告)日：2013-07-02

申请号：US13052238

申请日：2011-03-21

申请人： Sasha Kweskin ,  Hiroshi Hamana ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kadar Sapre

发明人： Sasha Kweskin ,  Hiroshi Hamana ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kadar Sapre

IPC分类号： H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/67017

摘要： Aspects of the disclosure pertain to methods of preferentially filling narrow trenches with silicon oxide while not completely filling wider trenches and/or open areas. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively dense first portion of a silicon oxide layer followed by a more porous (and more rapidly etched) second portion of the silicon oxide layer. Narrow trenches are filled with dense material whereas open areas are covered with a layer of dense material and more porous material. Dielectric material in wider trenches may be removed at this point with a wet etch while the dense material in narrow trenches is retained.

摘要翻译： 本公开的方面涉及优先用氧化硅填充窄沟槽而不完全填充较宽的沟槽和/或开放区域的方法。 在实施例中，通过使含硅前体和臭氧流入处理室来沉积电介质层，使得氧化硅层的相对致密的第一部分，随后是氧化硅层的更多孔（并且更快蚀刻）的第二部分 。 狭窄的沟槽填充有致密的材料，而开放区域被一层致密材料和更多孔的材料覆盖。 在较宽的沟槽中的电介质材料可以在这一点用湿法蚀刻去除，而狭窄沟槽中的致密材料被保留。

公开(公告)号：US20110223774A1

公开(公告)日：2011-09-15

申请号：US12855877

申请日：2010-08-13

申请人： Sasha Kweskin ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kedar Sapre

发明人： Sasha Kweskin ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kedar Sapre

IPC分类号： H01L21/316

CPC分类号： H01L21/02219 ,  C23C16/401 ,  H01L21/02164 ,  H01L21/02271

摘要： Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.

摘要翻译： 本公开的方面涉及在图案化衬底上沉积电介质层的方法。 在实施方案中，通过将BIS（二乙胺）硅烷（BDEAS），臭氧和分子氧流入处理室来沉积电介质层，使得跨越图案化的衬底表面实现相对均匀的电介质生长速率。 根据实施例生长的电介质层的沉积可以减少对图案密度的依赖性，同时仍然适用于非牺牲应用。

公开(公告)号：US20110250731A1

公开(公告)日：2011-10-13

申请号：US13052238

申请日：2011-03-21

申请人： Sasha Kweskin ,  Hiroshi Hamana ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kadar Sapre

发明人： Sasha Kweskin ,  Hiroshi Hamana ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kadar Sapre

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/67017

摘要： Aspects of the disclosure pertain to methods of preferentially filling narrow trenches with silicon oxide while not completely filling wider trenches and/or open areas. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively dense first portion of a silicon oxide layer followed by a more porous (and more rapidly etched) second portion of the silicon oxide layer. Narrow trenches are filled with dense material whereas open areas are covered with a layer of dense material and more porous material. Dielectric material in wider trenches may be removed at this point with a wet etch while the dense material in narrow trenches is retained.

摘要翻译： 本公开的方面涉及优先用氧化硅填充窄沟槽而不完全填充较宽的沟槽和/或开放区域的方法。 在实施例中，通过使含硅前体和臭氧流入处理室来沉积电介质层，使得氧化硅层的相对致密的第一部分，随后是氧化硅层的更多孔（并且更快蚀刻）的第二部分 。 狭窄的沟槽填充有致密的材料，而开放区域被一层致密材料和更多孔的材料覆盖。 在较宽的沟槽中的电介质材料可以在这一点用湿法蚀刻去除，而狭窄沟槽中的致密材料被保留。

公开(公告)号：US08236708B2

公开(公告)日：2012-08-07

申请号：US12855877

申请日：2010-08-13

申请人： Sasha Kweskin ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kedar Sapre

发明人： Sasha Kweskin ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kedar Sapre

IPC分类号： H01L21/316 ,  C23C16/40

CPC分类号： H01L21/02219 ,  C23C16/401 ,  H01L21/02164 ,  H01L21/02271

摘要： Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.

摘要翻译： 本公开的方面涉及在图案化衬底上沉积电介质层的方法。 在实施方案中，通过将BIS（二乙胺）硅烷（BDEAS），臭氧和分子氧流入处理室来沉积电介质层，使得跨越图案化的衬底表面实现相对均匀的电介质生长速率。 根据实施例生长的电介质层的沉积可以减少对图案密度的依赖性，同时仍然适用于非牺牲应用。

公开(公告)号：US07994019B1

公开(公告)日：2011-08-09

申请号：US12891149

申请日：2010-09-27

申请人： Sasha Kweskin ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kedar Sapre

发明人： Sasha Kweskin ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kedar Sapre

IPC分类号： H01L21/00

CPC分类号： H01L21/02164 ,  C23C16/401 ,  C23C16/45523 ,  H01L21/0228

摘要： Aspects of the disclosure pertain to methods of depositing conformal silicon oxide layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface having heterogeneous materials and/or a heterogeneous pattern density distribution. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on underlying material and pattern density while still being suitable for non-sacrificial applications. Reduction in dependence on pattern density is achieved by terminating deposition near the end of an incubation period. Multiple deposition cycles may be conducted in series since the beneficial nature of the incubation period may repeat after a pause in deposition.

摘要翻译： 本公开的方面涉及在图案化衬底上沉积保形氧化硅层的方法。 在实施例中，通过将含硅前体和臭氧流入处理室来沉积电介质层，使得跨越具有异质材料的图案化衬底表面和/或异质图案密度分布实现相对均匀的介电生长速率。 根据实施例生长的电介质层的沉积可以降低对下层材料和图案密度的依赖性，同时仍然适用于非牺牲应用。 依靠图案密度的减少是通过在潜伏期结束时终止沉积来实现的。 多个沉积循环可以串联进行，因为在沉积停顿之后潜伏期的有益特性可以重复。