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    Low complexity out-of-order issue logic using static circuits
    1.
    发明授权
    Low complexity out-of-order issue logic using static circuits 有权

    公开(公告)号：US09740494B2

    公开(公告)日：2017-08-22

    申请号：US13459964

    申请日：2012-04-30

    申请人： Lawrence T. Clark ,  Siddhesh Mhambrey ,  Satendra Kumar Maurya

    发明人： Lawrence T. Clark ,  Siddhesh Mhambrey ,  Satendra Kumar Maurya

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3836 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/3851

    摘要： Instruction issue circuits are disclosed that are configured to issue multiple instructions within a superscalar pipeline of a microprocessor. The instruction issue circuit includes an instruction queue that stores instructions. A ready generation circuit is operably associated with the instruction queue and generates ready signals that indicate which instructions in the instruction queue are ready for execution. To simplify the instruction issue circuit, the instruction issue circuit has group blocks. Each group block receives a different group of the ready signals corresponding to a different group of the instructions. Each group block generates a group output indicating a group set within the corresponding group of the instructions that has a highest instruction execution priority and are ready for execution. By splitting the ready signals into groups, the groups of ready signals can be processed in parallel thereby reducing both the resulting delay and complexity of the instruction issue circuit.

    LOW COMPLEXITY OUT-OF-ORDER ISSUE LOGIC USING STATIC CIRCUITS
    3.
    发明申请
    LOW COMPLEXITY OUT-OF-ORDER ISSUE LOGIC USING STATIC CIRCUITS 有权
    使用静态电路的低复杂度输出逻辑问题

    公开(公告)号：US20120278593A1

    公开(公告)日：2012-11-01

    申请号：US13459964

    申请日：2012-04-30

    申请人： Lawrence T. Clark ,  Siddhesh Mhambrey ,  Satendra Kumar Maurya

    发明人： Lawrence T. Clark ,  Siddhesh Mhambrey ,  Satendra Kumar Maurya

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3836 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/3851

    摘要： Instruction issue circuits are disclosed that are configured to issue multiple instructions within a superscalar pipeline of a microprocessor. The instruction issue circuit includes an instruction queue that stores instructions. A ready generation circuit is operably associated with the instruction queue and generates ready signals that indicate which instructions in the instruction queue are ready for execution. To simplify the instruction issue circuit, the instruction issue circuit has group blocks. Each group block receives a different group of the ready signals corresponding to a different group of the instructions. Each group block generates a group output indicating a group set within the corresponding group of the instructions that has a highest instruction execution priority and are ready for execution. By splitting the ready signals into groups, the groups of ready signals can be processed in parallel thereby reducing both the resulting delay and complexity of the instruction issue circuit.

    摘要翻译： 公开了指令发布电路，其被配置为在微处理器的超标量流水线内发出多个指令。 指令发布电路包括存储指令的指令队列。 准备生成电路与指令队列可操作地相关联，并产生指示指令队列中哪些指令准备好执行的就绪信号。 为了简化指令发布电路，指令发布电路具有组块。 每个组块接收对应于不同组指令的不同组的就绪信号。 每个组块产生指示在具有最高指令执行优先级并且准备好执行的指令的相应组内的组集合的组输出。 通过将准备好的信号分成组，准备信号组可以被并行处理，从而减少指令发出电路的延迟和复杂性。