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    Low complexity out-of-order issue logic using static circuits
    1.
    发明授权
    Low complexity out-of-order issue logic using static circuits 有权

    公开(公告)号：US09740494B2

    公开(公告)日：2017-08-22

    申请号：US13459964

    申请日：2012-04-30

    申请人： Lawrence T. Clark ,  Siddhesh Mhambrey ,  Satendra Kumar Maurya

    发明人： Lawrence T. Clark ,  Siddhesh Mhambrey ,  Satendra Kumar Maurya

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3836 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/3851

    摘要： Instruction issue circuits are disclosed that are configured to issue multiple instructions within a superscalar pipeline of a microprocessor. The instruction issue circuit includes an instruction queue that stores instructions. A ready generation circuit is operably associated with the instruction queue and generates ready signals that indicate which instructions in the instruction queue are ready for execution. To simplify the instruction issue circuit, the instruction issue circuit has group blocks. Each group block receives a different group of the ready signals corresponding to a different group of the instructions. Each group block generates a group output indicating a group set within the corresponding group of the instructions that has a highest instruction execution priority and are ready for execution. By splitting the ready signals into groups, the groups of ready signals can be processed in parallel thereby reducing both the resulting delay and complexity of the instruction issue circuit.

    LOW COMPLEXITY OUT-OF-ORDER ISSUE LOGIC USING STATIC CIRCUITS
    3.
    发明申请
    LOW COMPLEXITY OUT-OF-ORDER ISSUE LOGIC USING STATIC CIRCUITS 有权
    使用静态电路的低复杂度输出逻辑问题

    公开(公告)号：US20120278593A1

    公开(公告)日：2012-11-01

    申请号：US13459964

    申请日：2012-04-30

    申请人： Lawrence T. Clark ,  Siddhesh Mhambrey ,  Satendra Kumar Maurya

    发明人： Lawrence T. Clark ,  Siddhesh Mhambrey ,  Satendra Kumar Maurya

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3836 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/3851

    摘要： Instruction issue circuits are disclosed that are configured to issue multiple instructions within a superscalar pipeline of a microprocessor. The instruction issue circuit includes an instruction queue that stores instructions. A ready generation circuit is operably associated with the instruction queue and generates ready signals that indicate which instructions in the instruction queue are ready for execution. To simplify the instruction issue circuit, the instruction issue circuit has group blocks. Each group block receives a different group of the ready signals corresponding to a different group of the instructions. Each group block generates a group output indicating a group set within the corresponding group of the instructions that has a highest instruction execution priority and are ready for execution. By splitting the ready signals into groups, the groups of ready signals can be processed in parallel thereby reducing both the resulting delay and complexity of the instruction issue circuit.

    摘要翻译： 公开了指令发布电路，其被配置为在微处理器的超标量流水线内发出多个指令。 指令发布电路包括存储指令的指令队列。 准备生成电路与指令队列可操作地相关联，并产生指示指令队列中哪些指令准备好执行的就绪信号。 为了简化指令发布电路，指令发布电路具有组块。 每个组块接收对应于不同组指令的不同组的就绪信号。 每个组块产生指示在具有最高指令执行优先级并且准备好执行的指令的相应组内的组集合的组输出。 通过将准备好的信号分成组，准备信号组可以被并行处理，从而减少指令发出电路的延迟和复杂性。

    MULTI-MODE RADIATION HARDENED MULTI-CORE MICROPROCESSORS
    5.
    发明申请
    MULTI-MODE RADIATION HARDENED MULTI-CORE MICROPROCESSORS 审中-公开

    公开(公告)号：US20180046580A1

    公开(公告)日：2018-02-15

    申请号：US15672810

    申请日：2017-08-09

    申请人： Lawrence T. Clark

    发明人： Lawrence T. Clark

    IPC分类号： G06F12/0897

    摘要： Systems and methods for multi-mode radiation hardened multi-core microprocessors are disclosed. In some embodiments, a triplicated circuit includes a first core logic, a second core logic, a third core logic, and bus arbitration and control circuitry. The triplicated circuit is configurable to operate in both a Triple-Modular Redundant (TMR) mode of operation and a multi-threaded mode of operation. In some embodiments, there is essentially no overhead in soft mode and low overhead (power only) in hard mode. In most applications, it is expected that portions of missions require very hard systems (e.g., landing) where a failure is catastrophic. However, other portions require essentially no hardening (digital signal processor and signal processing activities) but much better throughput. Consequently, there is a huge opportunity to develop computer processors with low overhead in soft mode and unprecedented hardness in hard mode.

    RADIATION HARDENING ARCHITECTURAL EXTENSIONS FOR A RADIATION HARDENED BY DESIGN MICROPROCESSOR
    6.
    发明申请
    RADIATION HARDENING ARCHITECTURAL EXTENSIONS FOR A RADIATION HARDENED BY DESIGN MICROPROCESSOR 审中-公开
    通过设计微处理器硬化辐射的辐射硬化结构扩展

    公开(公告)号：US20160065243A1

    公开(公告)日：2016-03-03

    申请号：US14837361

    申请日：2015-08-27

    申请人： Dan Wheeler Patterson ,  Lawrence T. Clark

    发明人： Dan Wheeler Patterson ,  Lawrence T. Clark

    IPC分类号： H03M13/11 ,  G06F9/30 ,  H03M13/00

    CPC分类号： G06F9/30145 ,  G06F9/3861 ,  G06F9/3863 ,  G06F11/00

    摘要： This disclosure relates generally to processors and methods of operating the same. In particular, this disclosure relates to components for correcting soft errors in a processor. In one embodiment, a processor includes an instruction decoder and an exception handler. The instruction decoder is configured to receive one or more soft error correction instructions and decode the one or more soft error correction instructions. Additionally, an exception handler is configured to execute the one or more soft error correction instructions so as to correct one or more soft errors. In this manner, the processor is capable of correcting soft errors that are the result of radiation strikes.

    摘要翻译： 本公开一般涉及其操作处理器和方法。 特别地，本公开涉及用于校正处理器中的软错误的组件。 在一个实施例中，处理器包括指令解码器和异常处理程序。 指令解码器被配置为接收一个或多个软错误校正指令并对一个或多个软错误校正指令进行解码。 此外，异常处理程序被配置为执行一个或多个软错误校正指令，以便校正一个或多个软错误。 以这种方式，处理器能够校正作为辐射打击结果的软错误。

    Sequential state elements in triple-mode redundant (TMR) state machines
    7.
    发明授权
    Sequential state elements in triple-mode redundant (TMR) state machines 有权
    三模冗余（TMR）状态机中的顺序状态元素

    公开(公告)号：US09038012B2

    公开(公告)日：2015-05-19

    申请号：US14304155

    申请日：2014-06-13

    申请人： Lawrence T. Clark ,  Nathan D. Hindman ,  Dan Wheeler Patterson

    发明人： Lawrence T. Clark ,  Nathan D. Hindman ,  Dan Wheeler Patterson

    IPC分类号： G06F17/50 ,  H03K19/173 ,  H03K19/003

    CPC分类号： G06F17/5072 ,  G06F17/505 ,  H03K19/00315

    摘要： The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.

    摘要翻译： 本公开一般涉及形成为诸如CMOS的半导体衬底上的集成电路的三冗余顺序状态（TRSS）机器，以及设计三重冗余顺序状态机的计算机化方法和系统。 本公开中特别关注的是用于采样和保持位状态的顺序状态元素（SSE）。 位状态的采样和保持由时钟信号同步，从而允许在TRSS机器中流水线化。 具体地，时钟信号可以在第一时钟状态和第二时钟状态之间振荡，以根据由时钟状态提供的定时使SSE的操作同步。 SSEs具有自我纠正机制，可防止辐射诱发的软错误。 SSE可以设置在TRSS机器的管线电路中，以接收和存储由管线电路内的组合电路产生的位信号的位状态。

    Circuit devices and methods having adjustable transistor body bias
    8.
    发明授权
    Circuit devices and methods having adjustable transistor body bias 有权
    具有可调节晶体管体偏置的电路器件和方法

    公开(公告)号：US08995204B2

    公开(公告)日：2015-03-31

    申请号：US13167625

    申请日：2011-06-23

    申请人： Lawrence T. Clark ,  Bruce McWilliams ,  Robert Rogenmoser

    发明人： Lawrence T. Clark ,  Bruce McWilliams ,  Robert Rogenmoser

    IPC分类号： G11C7/00 ,  G11C11/412

    CPC分类号： G11C11/412

    摘要： Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.

    摘要翻译： 公开了电路，集成电路器件和方法，其可以包括具有位于栅极下方的屏蔽区域并通过半导体层与栅极分离的可偏置晶体管。 偏置电压可以应用于这样的屏蔽区域以优化多个性能特征，例如速度和电流泄漏。 特定实施例可以包括耦合在高电源电压和低电源电压之间的偏置部分，每个具有可偏置晶体管。 一个或多个发电电路可以产生多个偏置电压。 偏置控制部分可以将不同偏置电压之一耦合到可偏置晶体管的屏蔽区域，以提供用于这种最小速度的最小速度和最小电流泄漏。

    Methods and apparatus to selectively power functional units
    10.
    发明授权
    Methods and apparatus to selectively power functional units 有权
    选择性地为功能单元供电的方法和装置

    公开(公告)号：US08732490B1

    公开(公告)日：2014-05-20

    申请号：US13362358

    申请日：2012-01-31

    申请人： Dennis M. O'Connor ,  Michael W. Morrow ,  Lawrence T. Clark

    发明人： Dennis M. O'Connor ,  Michael W. Morrow ,  Lawrence T. Clark

    IPC分类号： G06F1/32 ,  G06F1/26

    CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3814 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3885 ,  G06F12/0875 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/171

    摘要： A processing engine fetches one or more lines of software instructions into an instruction cache. Based on the contents of the cache, potentially needed functional units are identified as functional units that are operable to execute at least one software instruction stored within the instruction cache. Unneeded functional units are identified as functional units that are not operable to execute a software instruction stored within the instruction cache. A power increase is initiated for selected ones of the potentially needed functional units that are determined to be in a low power state. A power decrease is initiated for selected ones of the unneeded functional units that are determined to be in an operable power state.

    摘要翻译： 处理引擎将一行或多行软件指令读取到指令高速缓存中。 基于高速缓存的内容，可能需要的功能单元被识别为可操作以执行存储在指令高速缓存内的至少一个软件指令的功能单元。 不需要的功能单元被识别为不能用于执行存储在指令高速缓存内的软件指令的功能单元。 对被确定为处于低功率状态的潜在需要的功能单元中的所选择的功能单元启动功率增加。 对被确定为处于可操作功率状态的不需要的功能单元中的所选功能单元启动功率减小。