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    RADIATION HARDENED DIGITAL CIRCUIT
    3.
    发明申请
    RADIATION HARDENED DIGITAL CIRCUIT 有权
    辐射硬化数字电路

    公开(公告)号：US20160028397A1

    公开(公告)日：2016-01-28

    申请号：US14808348

    申请日：2015-07-24

    申请人： Lawrence T. Clark

    发明人： Lawrence T. Clark

    IPC分类号： H03K19/003 ,  H03K3/2893 ,  H03K19/007

    CPC分类号： H03K19/0033 ,  H03K19/0075

    摘要： This disclosure relates generally to radiation hardened digital circuits. In one embodiment, a radiation hardened digital circuit includes a delay network and a first Muller C element. The delay network is configured to generate a first delayed clock signal from a global clock signal such that that the first delayed clock signal is delayed with respect to the global clock signal. The first Muller C element is configured to generate a first clock input signal and set the first clock input signal to one of a set of clock states in response to the first delayed clock signal and the global clock signal each being provided in a same one of the set of clock states and is configured to hold the first clock input signal otherwise. Thus, a radiation strike is prevented from causing a soft error in the first clock input signal.

    摘要翻译： 本公开一般涉及辐射硬化的数字电路。 在一个实施例中，辐射硬化的数字电路包括延迟网络和第一Muller C元件。 延迟网络被配置为从全局时钟信号产生第一延迟时钟信号，使得第一延迟时钟信号相对于全局时钟信号被延迟。 第一Muller C元件被配置为产生第一时钟输入信号，并且响应于第一延迟时钟信号和全局时钟信号将第一时钟输入信号设置为一组时钟状态中的一个，每个时钟信号分别以 一组时钟状态，并被配置为保持第一个时钟输入信号。 因此，防止辐射打击在第一时钟输入信号中引起软错误。

    STRUCTURES AND METHODS FOR DESIGN AUTOMATION OF RADIATION HARDENED TRIPLE MODE REDUNDANT DIGITAL CIRCUITS
    5.
    发明申请
    STRUCTURES AND METHODS FOR DESIGN AUTOMATION OF RADIATION HARDENED TRIPLE MODE REDUNDANT DIGITAL CIRCUITS 有权
    辐射硬化三重模式冗余数字电路设计自动化的结构与方法

    公开(公告)号：US20120306535A1

    公开(公告)日：2012-12-06

    申请号：US13487859

    申请日：2012-06-04

    申请人： Lawrence T. Clark ,  Nathan D. Hindman ,  Dan Wheeler Patterson

    发明人： Lawrence T. Clark ,  Nathan D. Hindman ,  Dan Wheeler Patterson

    IPC分类号： H03K19/173 ,  G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/505 ,  H03K19/00315

    摘要： The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. TheSSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.

    摘要翻译： 本公开一般涉及形成为诸如CMOS的半导体衬底上的集成电路的三冗余顺序状态（TRSS）机器，以及设计三重冗余顺序状态机的计算机化方法和系统。 本公开中特别关注的是用于采样和保持位状态的顺序状态元素（SSE）。 位状态的采样和保持由时钟信号同步，从而允许在TRSS机器中流水线化。 具体地，时钟信号可以在第一时钟状态和第二时钟状态之间振荡，以根据由时钟状态提供的定时使SSE的操作同步。 SSEs具有自我纠正机制，可防止辐射诱发的软错误。 SSE可以设置在TRSS机器的管线电路中，以接收和存储由管线电路内的组合电路产生的位信号的位状态。

    Power supply delivery for leakage suppression modes
    6.
    发明授权
    Power supply delivery for leakage suppression modes 有权
    泄漏抑制模式的电源输送

    公开(公告)号：US08307232B1

    公开(公告)日：2012-11-06

    申请号：US12887930

    申请日：2010-09-22

    申请人： Lawrence T. Clark

    发明人： Lawrence T. Clark

    IPC分类号： G06F1/26

    CPC分类号： H04B1/1615 ,  H04W52/028 ,  Y02D70/40

    摘要： A system including an integrated circuit (IC) and a power supply regulator external to the IC. The IC operates in accordance with an active mode and a lower power mode, and is configured to retain a logical state during the low power mode. The power supply regulator is configured to i) supply a first voltage potential to a first pin of the IC during the active mode, and ii) disable the first voltage potential during the low power mode. The IC is configured to provide a first feedback signal from an internal supply of the IC to the power supply regulator via the first pin.

    摘要翻译： 一种包括集成电路（IC）和IC外部的电源调节器的系统。 IC根据活动模式和较低功率模式工作，并且被配置为在低功率模式期间保持逻辑状态。 电源调节器被配置为i）在活动模式期间向IC的第一引脚提供第一电压电位，以及ii）在低功率模式期间禁用第一电压电位。 IC被配置为经由第一引脚将IC的内部电源的第一反馈信号提供给电源调节器。

    Two-dimensional parity technique to facilitate error detection and correction in memory arrays
    9.
    发明授权
    Two-dimensional parity technique to facilitate error detection and correction in memory arrays 有权
    二维奇偶校验技术，便于存储器阵列中的错误检测和校正

    公开(公告)号：US08122317B1

    公开(公告)日：2012-02-21

    申请号：US12163640

    申请日：2008-06-27

    申请人： Lawrence T. Clark ,  Karl C. Mohr

    发明人： Lawrence T. Clark ,  Karl C. Mohr

    IPC分类号： H03M13/00

    CPC分类号： H03M13/2909 ,  G06F11/1012

    摘要： The present invention is directed to a two-dimensional parity technique for data to be stored in one or more memory arrays, each of which has various rows and columns of cells. A row of bits in a super bundle is referred to as a row bundle. A super bundle includes numerous rows of row bundles, and corresponding bits in each of the row bundles in the super bundle are aligned in columns. A row check bit is provided for each row bundle in each super bundle. Each row check bit provides a parity bit that is derived from the k bits of the corresponding row bundle. A column check bit is provided for each column in each super bundle. Each column check bit provides a parity bit that is derived from each of the bits in the corresponding column in the super bundle.

    摘要翻译： 本发明涉及用于存储在一个或多个存储器阵列中的数据的二维奇偶校验技术，每个存储器阵列具有不同的行和列的单元。 超级捆绑中的一行位称为行捆绑。 超级捆绑包包括多行行束，并且超级捆绑中的每个行束中的相应位在列中对齐。 每个超级捆绑包中的每个行捆绑包都提供行检查位。 每行检查位提供从相应行束的k位导出的​​奇偶校验位。 每个超级包中的每列都提供列校验位。 每个列校验位提供从超级组中相应列中的每个位导出的奇偶校验位。

    SRAM cell with intrinsically high stability and low leakage
    10.
    发明授权
    SRAM cell with intrinsically high stability and low leakage 有权
    具有本质上高稳定性和低泄漏性的SRAM单元

    公开(公告)号：US07920409B1

    公开(公告)日：2011-04-05

    申请号：US11758568

    申请日：2007-06-05

    申请人： Lawrence T. Clark ,  Sayeed Ahmed Badrudduza

    发明人： Lawrence T. Clark ,  Sayeed Ahmed Badrudduza

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： A Static Random Access Memory (SRAM) cell having high stability and low leakage is provided. The SRAM cell includes a pair of cross-coupled inverters providing differential storage of a data bit. Power to the SRAM cell is provided by a read word line (RWL) signal, which is also referred to herein as a read control signal. During read operations, the RWL signal is pulled to a voltage level that forces the SRAM cell to a full-voltage state. During standby, the RWL signal is pulled to a voltage level that forces the SRAM cell to a voltage collapsed state in order to reduce leakage current, or leakage power, of the SRAM cell. A read-transistor providing access to the bit stored by the SRAM cell is coupled to the SRAM cell via a gate of the read transistor, thereby decoupling the stability of the SRAM cell from the read operation.

    摘要翻译： 提供了具有高稳定性和低泄漏的静态随机存取存储器（SRAM）单元。 SRAM单元包括一对交叉耦合的反相器，提供数据位的差分存储。 SRAM单元的电源由读取字线（RWL）信号提供，读取字线（RWL）信号在本文中也称为读取控制信号。 在读取操作期间，RWL信号被拉到一个电压电平，迫使SRAM单元达到全电压状态。 在待机期间，RWL信号被拉至电压电平，迫使SRAM单元处于电压合拢状态，以便降低SRAM单元的漏电流或泄漏功率。 提供对SRAM单元存储的位的访问的读晶体管经由读晶体管的栅极耦合到SRAM单元，从而将SRAM单元的稳定性与读操作分离。