公开(公告)号：US06374317B1

公开(公告)日：2002-04-16

申请号：US09414377

申请日：1999-10-07

申请人： Jasmin Ajanovic ,  Serafin Garcia ,  David J. Harriman

发明人： Jasmin Ajanovic ,  Serafin Garcia ,  David J. Harriman

IPC分类号： G06F1310

CPC分类号： G06F13/4045

摘要： According to one embodiment, a computer system includes a first hub agent and a hub interface coupled to the first hub agent. The first hub agent is adaptable to sample the hub interface in order to detect the presence of a second hub agent upon initiation of the computer system. In a further embodiment, the first hub agent comprises a presence detect module and control logic coupled to the presence detect module. The control logic responds to a central processing unit (CPU) poll request if the second hub agent is detected and does not respond to the CPU if the first device is not detected.

摘要翻译： 根据一个实施例，计算机系统包括耦合到第一集线器代理的第一集线器代理和集线器接口。 第一集线器代理适于对集线器接口进行采样，以便在计算机系统启动时检测第二集线器代理的存在。 在另一实施例中，第一集线器代理包括耦合到存在检测模块的存在检测模块和控制逻辑。 如果检测到第二集线器代理，则控制逻辑响应中央处理单元（CPU）轮询请求，如果未检测到第一设备，则该控制逻辑不响应CPU。

公开(公告)号：US06915407B2

公开(公告)日：2005-07-05

申请号：US10813145

申请日：2004-03-30

申请人： Srinivasan T. Rajappa ,  Romesh B. Trivedi ,  Rajagopal Subramanian ,  Zohar Bogin ,  Serafin Garcia

发明人： Srinivasan T. Rajappa ,  Romesh B. Trivedi ,  Rajagopal Subramanian ,  Zohar Bogin ,  Serafin Garcia

IPC分类号： G06F13/40 ,  G06F12/00

CPC分类号： G06F13/4054

摘要： A method and apparatus for a source synchronous address receiver for a system bus. In one embodiment, a flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin. Other embodiments are described and claimed.

摘要翻译： 一种用于系统总线的源同步地址接收器的方法和装置。 在一个实施例中，输入到存储器总线的系统总线地址之间的流通由两个输入来控制：一个是源同步地址选通，指示接收器锁存地址并存储数据，而另一个是协议信号， 表示地址转移的开始。 流通电路响应于数字地址选通信号和数字地址选择信号产生使能信号，以在接收到地址分组之前生成具有地址分组和使能的流通门的使能信号 信号作为输入。 数字地址数据包出现在地址引脚上时，流通门将数字地址数据包（交易地址）的第一个分量提供给芯片组。 描述和要求保护其他实施例。

公开(公告)号：US06748513B1

公开(公告)日：2004-06-08

申请号：US09665922

申请日：2000-09-20

申请人： Srinivasan T. Rajappa ,  Romesh B. Trivedi ,  Rajagopal Subramanian ,  Zohar Bogin ,  Serafin Garcia

发明人： Srinivasan T. Rajappa ,  Romesh B. Trivedi ,  Rajagopal Subramanian ,  Zohar Bogin ,  Serafin Garcia

IPC分类号： G06F1200

CPC分类号： G06F13/4054

摘要： A method and apparatus for a source synchronous address receiver for a system bus is described. A flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin.

摘要翻译： 描述了用于系统总线的源同步地址接收器的方法和装置。 输入到存储器总线的系统总线地址之间的流通由两个输入控制：一个是源同步地址选通，指示接收器锁存地址并存储数据，而另一个是协议信号， 地址转移。 流通电路响应于数字地址选通信号和数字地址选择信号产生使能信号，以在接收到地址分组之前生成具有地址分组和使能的流通门的使能信号 信号作为输入。 数字地址数据包出现在地址引脚上时，流通门将数字地址数据包（交易地址）的第一个分量提供给芯片组。