公开(公告)号：US06374317B1

公开(公告)日：2002-04-16

申请号：US09414377

申请日：1999-10-07

申请人： Jasmin Ajanovic ,  Serafin Garcia ,  David J. Harriman

发明人： Jasmin Ajanovic ,  Serafin Garcia ,  David J. Harriman

IPC分类号： G06F1310

CPC分类号： G06F13/4045

摘要： According to one embodiment, a computer system includes a first hub agent and a hub interface coupled to the first hub agent. The first hub agent is adaptable to sample the hub interface in order to detect the presence of a second hub agent upon initiation of the computer system. In a further embodiment, the first hub agent comprises a presence detect module and control logic coupled to the presence detect module. The control logic responds to a central processing unit (CPU) poll request if the second hub agent is detected and does not respond to the CPU if the first device is not detected.

摘要翻译： 根据一个实施例，计算机系统包括耦合到第一集线器代理的第一集线器代理和集线器接口。 第一集线器代理适于对集线器接口进行采样，以便在计算机系统启动时检测第二集线器代理的存在。 在另一实施例中，第一集线器代理包括耦合到存在检测模块的存在检测模块和控制逻辑。 如果检测到第二集线器代理，则控制逻辑响应中央处理单元（CPU）轮询请求，如果未检测到第一设备，则该控制逻辑不响应CPU。

公开(公告)号：US06256697B1

公开(公告)日：2001-07-03

申请号：US09223638

申请日：1998-12-30

申请人： Jasmin Ajanovic ,  David J. Harriman

发明人： Jasmin Ajanovic ,  David J. Harriman

IPC分类号： G06F1336

CPC分类号： G06F13/36

摘要： An apparatus for reusing arbitration signals to frame data transfers between hub agents is disclosed. The apparatus includes an arbitration signal output circuit to output a first request signal to indicate a data transfer. The apparatus further includes a data path input/output unit to output data to a data path during a period indicated by the arbitration signal.

摘要翻译： 公开了一种用于重用仲裁信号以组合集线器代理之间的数据传输的装置。 该装置包括仲裁信号输出电路，用于输出第一请求信号以指示数据传送。 该装置还包括数据路径输入/输出单元，用于在由仲裁信号指示的时段期间向数据路径输出数据。

公开(公告)号：US6092158A

公开(公告)日：2000-07-18

申请号：US874414

申请日：1997-06-13

申请人： David J. Harriman ,  Brian K. Langendorf ,  Jasmin Ajanovic

发明人： David J. Harriman ,  Brian K. Langendorf ,  Jasmin Ajanovic

IPC分类号： G06F13/16 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F13/1642

摘要： A method and apparatus for arbitrating between command streams. The method unblocks high priority commands which are blocked and then selects any remaining high priority commands. Normal priority commands are selected after the high priority commands. A memory controller described includes a command queue block having a plurality of command queues, each being coupled to receive a different type of command. The memory controller also includes arbitration logic which, among other things, selects high priority read commands before high priority write commands. Memory interface logic generates memory accesses performing commands selected by the arbitration logic.

摘要翻译： 一种用于在命令流之间进行仲裁的方法和装置。 该方法解除阻塞的高优先级命令，然后选择剩余的高优先级命令。 在优先级高的命令之后选择正常优先级命令。 所描述的存储器控​​制器包括具有多个命令队列的命令队列块，每个命令队列被耦合以接收不同类型的命令。 存储器控制器还包括仲裁逻辑，其中除了别的以外，在高优先级写入命令之前选择高优先级的读取命令。 存储器接口逻辑产生执行由仲裁逻辑选择的命令的存储器访问。

公开(公告)号：US20130132683A1

公开(公告)日：2013-05-23

申请号：US13713614

申请日：2012-12-13

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US06516375B1

公开(公告)日：2003-02-04

申请号：US09433275

申请日：1999-11-03

申请人： Jasmin Ajanovic ,  David J. Harriman ,  Serafin E. Garcia

发明人： Jasmin Ajanovic ,  David J. Harriman ,  Serafin E. Garcia

IPC分类号： G06F1310

CPC分类号： G06F13/4027 ,  Y10S370/912

摘要： A configuration access request packet is transmitted from a first hub agent onto a hub interface. The configuration access request packet comprises an address formatted in accordance with a peripheral component interconnect (PCI) specification. The configuration access request packet is received from the hub interface by a second hub agent.

摘要翻译： 配置接入请求分组从第一集线器代理发送到集线器接口。 配置接入请求分组包括根据外围组件互连（PCI）规范格式化的地址。 由第二集线器代理从集线器接口接收配置接入请求分组。

公开(公告)号：US06496895B1

公开(公告)日：2002-12-17

申请号：US09430996

申请日：1999-11-01

申请人： David J. Harriman ,  Jasmin Ajanovic

发明人： David J. Harriman ,  Jasmin Ajanovic

IPC分类号： G06F1300

CPC分类号： G06F13/387

摘要： A first control hub component, within a computer system, having a first logic to synchronize an internal clock generator of the first control hub with an external clock generator in response to the external clock generator transitioning to a high power state. In response to the internal clock generator being synchronized with the external clock generator, the first logic initiates the first control hub to transmit a request packet to a second control hub via an interface. The first logic monitors the interface for receipt of a completion packet in reply to the request packet, wherein in response to the completion packet the first control hub is operable to continue communication with the second hub via the interface.

摘要翻译： 计算机系统内的第一控制集线器组件具有第一逻辑，用于响应于外部时钟发生器转换到高功率状态，将第一控制集线器的内部时钟发生器与外部时钟发生器同步。 响应于与外部时钟发生器同步的内部时钟发生器，第一逻辑启动第一控制集线器以经由接口向第二控制集线器发送请求分组。 第一逻辑监视接口以接收到响应于请求分组的完成分组，其中响应于完成分组，第一控制中心可操作以经由接口继续与第二集线器通信。

公开(公告)号：US06175884B1

公开(公告)日：2001-01-16

申请号：US09186047

申请日：1998-11-03

申请人： David J. Harriman ,  Jasmin Ajanovic

发明人： David J. Harriman ,  Jasmin Ajanovic

IPC分类号： G06F300

CPC分类号： G06F13/4022 ,  G06F13/423

摘要： One embodiment of an apparatus for communicating transaction types between hubs in a computer system includes a data path input/output unit to output a packet header. The packet header includes a request/completion field to indicate whether the packet header is a request packet header or a completion packet header. The packet header also includes a read/write field to indicate whether the packet header is for a read packet or for a write packet. The read/write field further indicates whether a length of data is to follow the packet header. The packet header further includes a data length field to indicate the length of data.

摘要翻译： 用于在计算机系统中的集线器之间传送交易类型的装置的一个实施例包括输出分组报头的数据路径输入/输出单元。 分组报头包括请求/完成字段，用于指示分组报头是否是请求分组报头或完成分组报头。 分组报头还包括读/写字段，以指示分组报头是针对读分组还是用于写分组。 读/写字段进一步指示数据长度是否遵循分组报头。 分组报头还包括指示数据长度的数据长度字段。

公开(公告)号：US6145039A

公开(公告)日：2000-11-07

申请号：US186219

申请日：1998-11-03

申请人： Jasmin Ajanovic ,  David J. Harriman

发明人： Jasmin Ajanovic ,  David J. Harriman

IPC分类号： G06F13/42 ,  G06F13/10

CPC分类号： G06F13/4208

摘要： An interface to transfer data between a memory controller hub and an input/output (I/O) hub of a chipset within a computer system. One embodiment of the interface includes a bi-directional data signal path and a pair of source synchronous strobe signals. The data signal path transmits data in packets via split transactions. In addition, the packets include a request packet and a completion packet, if necessary. Furthermore, in one embodiment, the request packets include a transaction descriptor.

摘要翻译： 在计算机系统内的存储器控​​制器集线器和芯片组的输入/输出（I / O）集线器之间传送数据的接口。 接口的一个实施例包括双向数据信号路径和一对源同步选通信号。 数据信号路径通过分组事务发送数据包。 此外，如果需要，分组包括请求分组和完成分组。 此外，在一个实施例中，请求分组包括事务描述符。

公开(公告)号：US20130132636A1

公开(公告)日：2013-05-23

申请号：US13690931

申请日：2012-11-30

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F13/42

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US20130091317A1

公开(公告)日：2013-04-11

申请号：US13691016

申请日：2012-11-30

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F13/40

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.