CMOS embedded high voltage transistor
    1.
    发明授权
    CMOS embedded high voltage transistor 有权
    CMOS嵌入式高压晶体管

    公开(公告)号:US07592661B1

    公开(公告)日:2009-09-22

    申请号:US11489047

    申请日:2006-07-19

    IPC分类号: H01L27/108 H01L29/94

    摘要: A circuit having a high voltage, drain-extended (DE) metal-oxide-semiconductor (MOS) transistor and method for fabricating the same are provided. Generally, the circuit includes an n-channel (NMOS) transistor having: (i) a source and drain formed in a substrate, the source separated from the drain by a channel; and (ii) a diffused deep n-well (DNW) formed by a long, high temperature drive-in step. The DNW forms a drain-extension region for the NMOS transistor surrounding the drain and extending a predetermined distance into the channel. The drain extension region has a doping concentration lower than the source and drain to deplete during reverse biasing of the transistor, thereby raising a breakdown voltage of the transistor. Preferably, the circuit further includes a DE p-channel MOS (PMOS) transistor in which the DNW forms a well tub for the PMOS transistor, and a p-well in DNW forms a DE region therefore. Other embodiments are also disclosed.

    摘要翻译: 提供具有高电压,漏极延伸(DE)金属氧化物半导体(MOS)晶体管的电路及其制造方法。 通常,电路包括:n沟道(NMOS)晶体管,其具有:(i)在衬底中形成的源极和漏极,源极通过沟道与漏极分离; 和(ii)通过长的高温驱动步骤形成的扩散的深n阱(DNW)。 DNW形成了围绕漏极的NMOS晶体管的漏极扩展区域,并且将预定距离延伸到沟道中。 漏极延伸区域具有低于源极和漏极的掺杂浓度以在晶体管的反向偏置期间消耗,从而提高晶体管的击穿电压。 优选地,电路还包括DE p沟道MOS(PMOS)晶体管,其中DNW形成用于PMOS晶体管的阱槽,因此在DNW中的p阱形成DE区。 还公开了其他实施例。

    Method of forming semiconductor memory device with LDD
    2.
    发明授权
    Method of forming semiconductor memory device with LDD 有权
    用LDD形成半导体存储器件的方法

    公开(公告)号:US06323091B1

    公开(公告)日:2001-11-27

    申请号:US09354884

    申请日:1999-07-16

    IPC分类号: H01L218234

    摘要: A method for manufacturing a semiconductor device in which ROM programming ion implantation is performed by utilizing the same mask as used for implanting dopant in MOS transistors. The ROM programming ion implantation is conducted under the same conditions as the MOS transistor forming step. Only a single mask needs to be modified for the programming, thus reducing cost and complexity of manufacturing the device.

    摘要翻译: 一种制造半导体器件的方法,其中通过利用与用于在MOS晶体管中注入掺杂剂所用的掩模相同的掩模来执行ROM编程离子注入。 ROM编程离子注入在与MOS晶体管形成步骤相同的条件下进行。 需要对编程进行修改,从而降低了制造设备的成本和复杂性。