公开(公告)号：US12132105B2

公开(公告)日：2024-10-29

申请号：US17571949

申请日：2022-01-10

申请人： Samsung Electronics Co., Ltd.

发明人： Hojun Choi ,  Ji Seong Kim ,  Min Cheol Oh ,  Ki-Il Kim

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7827 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66666

摘要： There is provided a semiconductor device capable of improving electrical characteristics and integration density. The semiconductor device includes an active pattern protruding from a substrate, the active pattern including long sidewalls extending in a first direction and opposite to each other in a second direction, a lower epitaxial pattern on the substrate and covering a part of the active pattern, a gate electrode on the lower epitaxial pattern and extending along the long sidewalls of the active pattern, and an upper epitaxial pattern on the active pattern and connected to an upper surface of the active pattern. The active pattern includes short sidewalls connecting with the long sidewalls of the active pattern, and at least one of the short sidewalls of the active pattern has a curved surface.

公开(公告)号：US20240355893A1

公开(公告)日：2024-10-24

申请号：US18204644

申请日：2023-06-01

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kai-Kuen CHANG

IPC分类号： H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/42368 ,  H01L27/088 ,  H01L29/66477 ,  H01L29/7838

摘要： A semiconductor structure includes a substrate and a first switch element disposed in a first device area of the substrate. The first switch element includes a channel region, a first gate dielectric layer, a first gate layer and a source/drain region. The channel region is disposed at the bottom of a recess in the first device area. The first gate dielectric layer has a first region and a second region extending into the recess, the first region has a first thickness; the second region has a second thickness, and the first thickness is smaller than the second thickness. The first gate layer is disposed above the first gate dielectric layer. The source/drain region is disposed in the substrate and adjacent to the first gate dielectric layer.

公开(公告)号：US20240322044A1

公开(公告)日：2024-09-26

申请号：US18734635

申请日：2024-06-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Cheng Chiang ,  Chi-Wen Liu ,  Ying-Keung Leung

IPC分类号： H01L29/78 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/7856 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78696 ,  H01L29/165 ,  H01L2029/7858

摘要： A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.

公开(公告)号：US12094945B2

公开(公告)日：2024-09-17

申请号：US17452788

申请日：2021-10-29

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Daejoong Won ,  Soonbyung Park ,  Er-Xuan Ping

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/4236 ,  H01L29/0607 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/66621 ,  H01L29/7825

摘要： A semiconductor structure and a forming method thereof are disclosed in the embodiments of the present disclosure. The semiconductor structure includes: a base, wherein a gate dielectric layer defining a groove is provided in the base, a source region and a drain region are located on two opposite sides at a top of the groove, and the groove has an extension direction parallel to a surface of the base; a first gate, including a first work function layer and a first conductive layer, wherein the first work function layer covers a bottom surface and partial sidewall of the groove, and the first conductive layer covers a surface of the first work function layer; and a second gate, including a second work function layer and a second conductive layer, wherein the second gate is laminated on the first gate and has a top surface lower than the surface of the base.

公开(公告)号：US20240276714A1

公开(公告)日：2024-08-15

申请号：US18635924

申请日：2024-04-15

申请人： Micron Technology, Inc.

发明人： Toshihiko Miyashita ,  Dan Mocuta

IPC分类号： H10B12/00 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H10B12/50 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/7851 ,  H10B12/09

摘要： DRAM circuitry comprises a memory array comprising memory cells individually comprising a transistor and a charge-storage device. The transistors individually comprise two source/drain regions having a gate there-between that is part of one of multiple wordlines of the memory array. One of the source/drain regions is electrically coupled to one of the charge-storage devices. The other of the source/drain regions is electrically coupled to one of multiple sense lines of the memory array. Peripheral circuitry comprises wordline-driver transistors having gates which individually comprise one of the wordlines and comprises sense-line-amplifier transistors having gates which individually comprise one of the sense lines. The sense-line-amplifier transistors and the wordline-driver transistors individually are a finFET having at least one fin comprising a channel region of the respective finFET. The sense-line-amplifier transistors and the wordline-driver transistors individually comprise two source/drain regions that individually comprise conductively-doped epitaxial semiconductor material that is adjacent one of two laterally-opposing sides of the at least one fin in a vertical cross-section. Methods are also disclosed.

公开(公告)号：US12052861B2

公开(公告)日：2024-07-30

申请号：US18321487

申请日：2023-05-22

申请人： STMicroelectronics (Rousset) SAS

发明人： François Tailliet

IPC分类号： H01L21/00 ,  G11C7/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H10B41/00 ,  H10B41/35 ,  H01L29/788

CPC分类号： H10B41/00 ,  G11C7/18 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66825 ,  H10B41/35 ,  H01L29/7881

摘要： An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.

公开(公告)号：US12046630B2

公开(公告)日：2024-07-23

申请号：US17452160

申请日：2021-10-25

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Qiang Wan ,  Kangshu Zhan ,  Jun Xia ,  Sen Li ,  Penghui Xu ,  Tao Liu

IPC分类号： H01L29/94 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/76

CPC分类号： H01L29/0649 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368

摘要： The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method includes: providing a base, wherein the base is provided with an active region; forming a gate layer on the base; forming isolation structures on a periphery of the gate layer, wherein in a direction away from the gate layer, each of the isolation structures at least includes a hollow portion and an isolation portion; forming an insulating structure on top surfaces of the isolation structures; forming contact plugs, wherein the contact plugs penetrate the insulating structure; an end of each of the contact plugs close to the base is electrically connected to the active region; each of the contact plugs is located on a side of each of the isolation structures away from the gate layer.

公开(公告)号：US12034074B2

公开(公告)日：2024-07-09

申请号：US17516017

申请日：2021-11-01

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Marie Denison ,  Sameer Pendharkar ,  Guru Mathur

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/42368 ,  H01L29/4238

摘要： A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

公开(公告)号：US20240194738A1

公开(公告)日：2024-06-13

申请号：US18587981

申请日：2024-02-27

申请人： UNITED MICROELECTRONICS CORP

发明人： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC分类号： H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/665

摘要： A semiconductor device includes a gate structure on a substrate, a spacer around the gate structure, and a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

公开(公告)号：US20240113187A1

公开(公告)日：2024-04-04

申请号：US18150266

申请日：2023-01-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jhu-Min Song ,  Ying-Chou Chen ,  Yi-Kai Ciou ,  Chien-Chih Chou ,  Fei-Yun Chen ,  Yu-Chang Jong ,  Chi-Te Lin

IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L29/42368 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/78

摘要： The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.