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公开(公告)号:US20190189803A1
公开(公告)日:2019-06-20
申请号:US16271226
申请日:2019-02-08
申请人: Intel Corporation
发明人: Grant KLOSTER , Scott B. CLENDENNING , Rami HOURANI , Szuya S. LIAO , Patricio E. ROMERO , Florian GSTREIN
IPC分类号: H01L29/78 , H01L21/32 , H01L21/3105 , H01L21/28 , H01L29/51 , H01L29/66 , H01L29/423 , H01L29/06 , H01L29/786 , H01L21/311 , H01L21/02
CPC分类号: H01L29/7851 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28194 , H01L21/3105 , H01L21/31058 , H01L21/31133 , H01L21/32 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L29/0649 , H01L29/0673 , H01L29/42368 , H01L29/42392 , H01L29/517 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/786 , H01L29/78696
摘要: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.
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公开(公告)号:US20190189798A1
公开(公告)日:2019-06-20
申请号:US16272601
申请日:2019-02-11
发明人: Yoshito NAKAZAWA , Yuji YATSUDA
IPC分类号: H01L29/78 , H01L29/66 , H01L27/02 , H01L29/49 , H01L29/423 , H01L21/285 , H01L21/28 , H01L29/40 , H01L29/06
CPC分类号: H01L29/7808 , H01L21/28008 , H01L21/28556 , H01L27/0255 , H01L29/0696 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/456 , H01L29/4916 , H01L29/66484 , H01L29/66545 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L29/7813
摘要: A semiconductor device including a field-effect transistor having source and drain source regions, first and second gate electrodes and a protective diode connected to the transistor. The first gate electrode is formed over a first gate insulating film in a lower part of a trench. The second gate electrode is formed over a second gate insulating film in an upper part of the trench. The first gate electrode includes a first polysilicon film, and the second gate electrode includes a second polysilicon film, wherein an impurity concentration of the first polysilicon film is lower than an impurity concentration of the second polysilicon film.
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公开(公告)号:US20190189779A1
公开(公告)日:2019-06-20
申请号:US15842899
申请日:2017-12-15
发明人: Ming LI , Jeoung Mo KOO , Raj Verma PURAKH
IPC分类号: H01L29/66 , H01L21/762 , H01L29/10 , H01L29/423 , H01L29/49 , H01L29/08 , H01L21/265 , H01L21/02 , H01L29/78 , H01L29/06 , H01L21/28 , H01L29/36
CPC分类号: H01L29/66681 , H01L21/02238 , H01L21/26513 , H01L21/266 , H01L21/28035 , H01L21/31053 , H01L21/32137 , H01L21/76224 , H01L21/76229 , H01L22/26 , H01L27/092 , H01L29/063 , H01L29/0649 , H01L29/0865 , H01L29/0882 , H01L29/1095 , H01L29/36 , H01L29/402 , H01L29/42368 , H01L29/42376 , H01L29/4916 , H01L29/7816
摘要: A method for forming a high voltage device is disclosed. The method comprises providing a substrate defined with a high voltage device region. A device well is formed to encompass the high voltage device region. A drift region is formed within the device well. A body well is formed within the device well adjacent to the drift region. A variable thickness gate dielectric is formed on the substrate. Forming the variable thickness gate dielectric comprises patterned a sacrificial polysilicon layer and oxidizing the patterned sacrificial polysilicon layer to define a thick gate oxide having sloped sidewalls. A gate electrode is formed on the variable thickness gate dielectric, wherein the gate electrode partially overlaps the thick gate oxide. A first and a second source/drain (S/D) region is formed adjacent to first and second sides of the variable thickness gate dielectric.
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公开(公告)号:US20190189737A1
公开(公告)日:2019-06-20
申请号:US16275469
申请日:2019-02-14
发明人: Makoto KOSHIMIZU , Hideki NIWAYAMA , Kazuyuki UMEZU , Hiroki SOEDA , Atsushi TACHIGAMI , Takeshi IIJIMA
IPC分类号: H01L29/06 , H01L21/762 , H01L21/8238 , H01L29/78 , H01L29/66 , H01L27/092 , H01L29/423
CPC分类号: H01L29/0649 , H01L21/76205 , H01L21/76224 , H01L21/82385 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L29/0638 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/086 , H01L29/0878 , H01L29/1083 , H01L29/41758 , H01L29/42368 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.
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公开(公告)号:US20190140004A1
公开(公告)日:2019-05-09
申请号:US16221850
申请日:2018-12-17
发明人: Feng-Chi Hung , Jhy-Jyi Sze , Shou-Gwo Wuu
IPC分类号: H01L27/146 , H01L29/66 , H01L21/265 , H01L21/266 , H01L21/762 , H01L29/06 , H01L29/417 , H01L29/423 , H01L21/02 , H01L29/78 , H01L21/28
CPC分类号: H01L27/14616 , H01L21/0223 , H01L21/26506 , H01L21/26586 , H01L21/266 , H01L21/28123 , H01L21/2822 , H01L21/76224 , H01L27/14603 , H01L27/14612 , H01L27/1463 , H01L29/0653 , H01L29/41775 , H01L29/42368 , H01L29/66568 , H01L29/78
摘要: Semiconductor devices and methods of forming semiconductor devices are disclosed. In some embodiments, a first trench and a second trench are formed in a substrate, and dopants of a first conductivity type are implanted along sidewalls and a bottom of the first trench and the second trench. The first and second trenches are filled with an insulating material, and a gate dielectric and a gate electrode over the substrate, the gate dielectric and the gate electrode extending over the first trench and the second trench. Source/drain regions are formed in the substrate on opposing sides of the gate dielectric and the gate electrode.
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公开(公告)号:US20190123155A1
公开(公告)日:2019-04-25
申请号:US15788216
申请日:2017-10-19
发明人: Jun CAI
CPC分类号: H01L29/408 , H01L21/02238 , H01L21/2652 , H01L21/26586 , H01L21/32 , H01L29/063 , H01L29/0653 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要: In accordance with at least one embodiment of the invention, a transistor comprises a semiconductor, a first drift layer, a drain region, a body region, a source region, a shallow trench isolation region, a dielectric, and a gate. The first drift layer is formed in the semiconductor and has majority carriers of a first type. The drain region is formed in the first drift layer and has majority carriers of the first type. The body region is formed in the semiconductor and has majority carriers of a second type. The source region is formed in the body region and has majority carriers of the first type. The shallow trench isolation region is formed in the first drift layer and disposed between the drain region and the body region. The dielectric is formed on the semiconductor, and the gate is formed over the dielectric and has a lift-up region.
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公开(公告)号:US20190088759A1
公开(公告)日:2019-03-21
申请号:US16080824
申请日:2016-04-01
申请人: INTEL CORPORATION
IPC分类号: H01L29/49 , H01L29/423
CPC分类号: H01L29/4983 , H01L21/28114 , H01L29/42368 , H01L29/42376 , H01L29/42392 , H01L29/66545 , H01L29/66553 , H01L29/66606 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/7856
摘要: Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.
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公开(公告)号:US20190035783A1
公开(公告)日:2019-01-31
申请号:US16140821
申请日:2018-09-25
发明人: Young Bae KIM , Kwang Il KIM , Jun Hyun KIM , In Sik JUNG , Jae Hyung JANG , Jin Yeong SON
IPC分类号: H01L27/088 , H01L29/66 , H01L21/8234 , H01L29/08 , H01L29/78 , H01L21/28 , H01L29/423 , H01L21/761 , H01L29/49
CPC分类号: H01L27/088 , H01L21/28247 , H01L21/761 , H01L21/764 , H01L21/823418 , H01L21/823462 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.
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公开(公告)号:US20190013403A1
公开(公告)日:2019-01-10
申请号:US16123253
申请日:2018-09-06
发明人: Young Bae KIM
IPC分类号: H01L29/78 , H01L29/808 , H01L29/66 , H01L29/40 , H01L29/06 , H01L29/417 , H01L27/085 , H01L29/10 , H01L29/423
CPC分类号: H01L29/7832 , H01L27/085 , H01L29/063 , H01L29/0649 , H01L29/0688 , H01L29/0696 , H01L29/1045 , H01L29/1058 , H01L29/1066 , H01L29/402 , H01L29/41758 , H01L29/42368 , H01L29/66659 , H01L29/66901 , H01L29/7835 , H01L29/808 , H02M7/00
摘要: Described is a semiconductor device including a first N-type well region disposed in a substrate and a second N-type well region in contact with the first N-type well region, a source region disposed in the first N-type well region, a drain region disposed in the second N-type well region, and a first gate electrode and a second gate electrode disposed spaced apart from the drain region. A maximum vertical length of the source region in a direction vertical to the first or second gate electrode is greater than a maximum vertical length of the drain region in the direction in a plan view.
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公开(公告)号:US20180366561A1
公开(公告)日:2018-12-20
申请号:US15626278
申请日:2017-06-19
申请人: NXP B.V.
CPC分类号: H01L29/66681 , H01L27/1203 , H01L29/0847 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/7824 , H01L29/7835
摘要: Described herein is an N type extended drain transistor formed from a semiconductor on insulator (SOI) wafer. The transistor has a buried P type region formed by the selective implantation of P type dopants in a semiconductor layer of the wafer at a location directly below a drift region of the transistor. The transistor also includes a source located in a P well region and a drain. The buried P type region is in electrical contact with the P well region. The N type drift region, the source, and the drain are also located in a portion of the semiconductor layer surrounded by dielectric isolation. A buried dielectric layer located below the portion of the semiconductor layer electrically isolates the portion of the semiconductor layer from a semiconductor substrate located below the buried dielectric layer.
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