公开(公告)号：US12223324B2

公开(公告)日：2025-02-11

申请号：US17957604

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael Estlick ,  Eric Dixon ,  Theodore Carlson ,  Erik D. Swanson

IPC: G06F9/38 ,  G06F9/30

Abstract: A data processing system includes a vector data processing unit that includes a shared scheduler queue configured to store in a same queue, at least one entry that includes at least a mask type instruction and another entry that includes at least a vector type instruction. Shared pipeline control logic controls a vector data path or a mask data path, based a type of instruction picked from the same queue. In some examples, at least one mask type instruction and the at least one vector type instruction each include a source operand having a corresponding shared source register bit field that indexes into both a mask register file and a vector register file. The shared pipeline control logic uses a mask register file or a vector register file depending on whether bits of the shared source register bit field identify a mask source register or a vector source register.

公开(公告)号：US10776123B2

公开(公告)日：2020-09-15

申请号：US16207548

申请日：2018-12-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Erik D. Swanson ,  Michael Estlick ,  Sneha V. Desai

IPC: G06F9/38

Abstract: Systems, apparatuses, and methods for performing efficient processor pipeline flush recovery are disclosed. A processor core includes a retire queue for storing information of outstanding instructions. When the retire queue logic detects that a pipeline flush condition occurs, the logic creates one or more groups of entries in the retire queue. The logic begins the groups with an entry storing information for a youngest outstanding instruction, and creates other groups in a contiguous manner after creating this first group. The logic marks with a first indication a given group when the given group includes one or more instructions of a given type. The logic marks with a second indication the given group when the given group does not include an instruction of the given type. The logic sends to flush recovery logic information of one or more entries in only groups marked with the first indication.

公开(公告)号：US20200174796A1

公开(公告)日：2020-06-04

申请号：US16207548

申请日：2018-12-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Erik D. Swanson ,  Michael Estlick ,  Sneha V. Desai

IPC: G06F9/38 ,  G06F9/30

Abstract: Systems, apparatuses, and methods for performing efficient processor pipeline flush recovery are disclosed. A processor core includes a retire queue for storing information of outstanding instructions. When the retire queue logic detects that a pipeline flush condition occurs, the logic creates one or more groups of entries in the retire queue. The logic begins the groups with an entry storing information for a youngest outstanding instruction, and creates other groups in a contiguous manner after creating this first group. The logic marks with a first indication a given group when the given group includes one or more instructions of a given type. The logic marks with a second indication the given group when the given group does not include an instruction of the given type. The logic sends to flush recovery logic information of one or more entries in only groups marked with the first indication.