公开(公告)号：US20210182072A1

公开(公告)日：2021-06-17

申请号：US16713432

申请日：2019-12-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexander Fuad ASHKAR ,  Manu RASTOGI ,  Harry J. WISE

IPC: G06F9/38 ,  G06F15/80 ,  G06T1/20

Abstract: A system includes a processing unit such as a GPU that itself includes a command processor configured to receive instructions for execution from a software application. A processor pipeline coupled to the processing unit includes a set of parallel processing units for executing the instructions in sets. A set manager is coupled to one or more of the processor pipeline and the command processor. The set manager includes at least one table for storing a set start time, a set end time, and a set execution time. The set manager determines an execution time for one or more sets of instructions of a first window of sets of instructions submitted to the processor pipeline. Based on the execution time of the one or more sets of instructions, a set limit is determined and applied to one or more sets of instructions of a second window subsequent to the first window.

公开(公告)号：US20220091847A1

公开(公告)日：2022-03-24

申请号：US17029841

申请日：2020-09-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexander Fuad ASHKAR ,  Harry J. WISE ,  Rex Eldon MCCRARY ,  Hans FERNLUND

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/54 ,  G06F13/16

Abstract: In response to executing a specified command packet, a processing unit prefetches commands stored at an indirect buffer a command queue for execution, prior to executing a command that initiates execution of the commands stored at the indirect buffer. By prefetching the data prior to executing the indirect buffer execution command, the processing unit reduces delays in processing the commands stored at the indirect buffer.

公开(公告)号：US20200379792A1

公开(公告)日：2020-12-03

申请号：US16427407

申请日：2019-05-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexander Fuad ASHKAR ,  Rakan KHRAISHA ,  Rex Eldon MCCRARY ,  Harry J. WISE

IPC: G06F9/455

Abstract: A processing unit employs microcode wherein the jump table associated with the microcode is embedded in the microcode itself. When the microcode is compiled based on a set of programmer instructions, the compiler prepares the jump table for the microcode and stores the jump table in the same file or other storage unit as the microcode. When the processing unit is initialized to execute a program, such as an operating system, the processing unit retrieves the microcode corresponding to the program from memory, stores the microcode in a cache or other memory module for execution, and automatically loads the embedded jump table from the microcode to a specified set of jump table registers, thereby preparing the processing unit to process received packets.

公开(公告)号：US20220100856A1

公开(公告)日：2022-03-31

申请号：US17032969

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Harry J. WISE ,  Alexander FUAD ASHKAR ,  Manu RASTOGI

IPC: G06F21/56 ,  H04L29/06 ,  G06F21/54 ,  G06F9/38 ,  G06F9/30

Abstract: A method of packet attribute confirmation includes receiving, at a command processor of a parallel processor, a command packet including a received packet attribute, such as a packet size, of the command packet. The command processor compares the received packet attribute of the command packet relative to an expected packet attribute of the command packet. The command processor passes one or more commands to a prefetch parser such that a summed total size of the one or more commands is equal to the received packet size of the command packet. The command processor passes, based at least on determining a match between the received packet size and the expected packet size, the received command packet to the prefetch parser. Otherwise, the command processor passes, based at least on determining a mismatch between the received packet size and the expected packet size, one or more no-operation instructions to the prefetch parser.

公开(公告)号：US20210181973A1

公开(公告)日：2021-06-17

申请号：US16710563

申请日：2019-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexander Fuad ASHKAR ,  James R. KLOBCAR ,  Harry J. WISE

IPC: G06F3/06 ,  G11C15/04

Abstract: A processing system includes a content addressable memory (CAM) in an input/output path to selectively modify register writes on a per-pipeline basis. The CAM compares an address of a register write to an address field of each entry of the CAM. If a match is found, the CAM modifies the register write data as defined by a function for the matching entry of the CAM. In some embodiments, each entry of the CAM includes a data mask defining subfields of the register write data, wherein each subfield includes subfield data including one or more bits.

公开(公告)号：US20200379767A1

公开(公告)日：2020-12-03

申请号：US16426613

申请日：2019-05-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rex Eldon MCCRARY ,  Yi LUO ,  Harry J. WISE ,  Alexander Fuad ASHKAR ,  Michael MANTOR

IPC: G06F9/38 ,  G06F16/245 ,  G06T1/20 ,  G06T1/60

Abstract: A method of context bouncing includes receiving, at a command processor of a graphics processing unit (GPU), a conditional execute packet providing a hash identifier corresponding to an encapsulated state. The encapsulated state includes one or more context state packets following the conditional execute packet. A command packet following the encapsulated state is executed based at least in part on determining whether the hash identifier of the encapsulated state matches one of a plurality of hash identifiers of active context states currently stored at the GPU.