公开(公告)号：US20210056031A1

公开(公告)日：2021-02-25

申请号：US17091993

申请日：2020-11-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William L. WALKER ,  Michael L. GOLDEN ,  Marius EVERS

IPC: G06F12/0862 ,  G06F12/128 ,  G06F12/1027 ,  G06F1/3234 ,  G06F12/0815 ,  G06F12/1009 ,  G06F12/0811

Abstract: A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.

公开(公告)号：US20190129853A1

公开(公告)日：2019-05-02

申请号：US15800727

申请日：2017-11-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William L. WALKER ,  Michael L. GOLDEN ,  Marius EVERS

IPC: G06F12/0862 ,  G06F12/128 ,  G06F12/1027 ,  G06F1/32 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/1009

Abstract: A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.