公开(公告)号：US20200293445A1

公开(公告)日：2020-09-17

申请号：US16355168

申请日：2019-03-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mohamed Assem IBRAHIM ,  Onur KAYIRAN ,  Yasuko ECKERT ,  Gabriel H. LOH

IPC: G06F12/0802

Abstract: A method of dynamic cache configuration includes determining, for a first clustering configuration, whether a current cache miss rate exceeds a miss rate threshold. The first clustering configuration includes a plurality of graphics processing unit (GPU) compute units clustered into a first plurality of compute unit clusters. The method further includes clustering, based on the current cache miss rate exceeding the miss rate threshold, the plurality of GPU compute units into a second clustering configuration having a second plurality of compute unit clusters fewer than the first plurality of compute unit clusters.

公开(公告)号：US20180285264A1

公开(公告)日：2018-10-04

申请号：US15475435

申请日：2017-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Onur KAYIRAN ,  Gabriel H. LOH ,  Yasuko ECKERT

IPC: G06F12/0806

CPC classification number: G06F12/0806 ,  G06F2212/621

Abstract: A processing system includes at least one central processing unit (CPU) core, at least one graphics processing unit (GPU) core, a main memory, and a coherence directory for maintaining cache coherence. The at least one CPU core receives a CPU cache flush command to flush cache lines stored in cache memory of the at least one CPU core prior to launching a GPU kernel. The coherence directory transfers data associated with a memory access request by the at least one GPU core from the main memory without issuing coherence probes to caches of the at least one CPU core.