公开(公告)号：US20250110792A1

公开(公告)日：2025-04-03

申请号：US18374263

申请日：2023-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Stephen Alexander Zekany ,  Anthony Thomas Gutierrez

IPC: G06F9/50

Abstract: In accordance with the described techniques, a host processor receives a task graph including tasks and indicating dependencies between the task graph. The host processor formats the task graph, in part, by sorting the tasks of the task graph in an order based on the dependencies between the tasks. Further, the host processor submits the formatted task graph to a scalable input/output virtualization (SIOV) device, which directs the SIOV device to process the tasks of the task graph based on the order.

公开(公告)号：US20250004806A1

公开(公告)日：2025-01-02

申请号：US18216310

申请日：2023-06-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mark Unruh Wyse ,  Anthony Thomas Gutierrez ,  Stephen Alexander Zekany ,  Paul Blinzer

IPC: G06F9/455

Abstract: A processing unit (e.g., a CPU) executes multiple processes, such as multiple virtual machines, wherein each process employs virtual signals and virtual signal monitors to support signaling between the process and one or more accelerators. A hardware signal manager (HSM) assigns each virtual signal to a physical signal of the system and assigns each virtual signal monitor to a physical signal monitor. Based on a process' interactions (e.g., signal operations) with a virtual signal monitor, the HSM executes corresponding interactions at the assigned physical signal monitor. The HSM thus virtualizes the physical signal monitors for the executing processes.