公开(公告)号：US20210182193A1

公开(公告)日：2021-06-17

申请号：US16713940

申请日：2019-12-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Weon Taek NA ,  Jagadish B. KOTRA ,  Yasuko ECKERT ,  Steven RAASCH ,  Sergey BLAGODUROV

IPC: G06F12/0811 ,  G06F12/0871 ,  G06F12/0831 ,  G06F12/0882 ,  G06F12/1027 ,  G06F9/30

Abstract: A processing system selectively allocates space to store a group of one or more cache lines at a cache level of a cache hierarchy having a plurality of cache levels based on memory access patterns of a software application executing at the processing system. The processing system generates bit vectors indicating which cache levels are to allocate space to store groups of one or more cache lines based on the memory access patterns, which are derived from data granularity and movement information. Based on the bit vectors, the processing system provides hints to the cache hierarchy indicating the lowest cache level that can exploit the reuse potential for a particular data.