公开(公告)号：US20200278930A1

公开(公告)日：2020-09-03

申请号：US16821632

申请日：2020-03-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Yasuko ECKERT ,  Maurice B. STEINMAN ,  Steven RAASCH

IPC: G06F12/0817 ,  G06F12/084

Abstract: A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.

公开(公告)号：US20210182193A1

公开(公告)日：2021-06-17

申请号：US16713940

申请日：2019-12-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Weon Taek NA ,  Jagadish B. KOTRA ,  Yasuko ECKERT ,  Steven RAASCH ,  Sergey BLAGODUROV

IPC: G06F12/0811 ,  G06F12/0871 ,  G06F12/0831 ,  G06F12/0882 ,  G06F12/1027 ,  G06F9/30

Abstract: A processing system selectively allocates space to store a group of one or more cache lines at a cache level of a cache hierarchy having a plurality of cache levels based on memory access patterns of a software application executing at the processing system. The processing system generates bit vectors indicating which cache levels are to allocate space to store groups of one or more cache lines based on the memory access patterns, which are derived from data granularity and movement information. Based on the bit vectors, the processing system provides hints to the cache hierarchy indicating the lowest cache level that can exploit the reuse potential for a particular data.

公开(公告)号：US20210182206A1

公开(公告)日：2021-06-17

申请号：US16712129

申请日：2019-12-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Steven RAASCH ,  Andrew G. KEGEL

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/123 ,  G06F12/0882 ,  G06F12/0871 ,  G06F12/02 ,  G06F11/07 ,  G06F9/50

Abstract: A processing system includes a primary processor and a co-processor. The primary processor is couplable to a memory subsystem having at least one memory and operating to execute system software employing memory address translations based on one or more page tables stored in the memory subsystem. The co-processor is likewise couplable to the memory subsystem and operates to perform iterations of a page table walk through one or more page tables maintained for the memory subsystem and to perform one or more page management operations on behalf of the system software based the iterations of the page table walk. The page management operations performed by the co-processor include analytic data aggregation, free list management and page allocation, page migration management, page table error detection, and the like.

公开(公告)号：US20240119010A1

公开(公告)日：2024-04-11

申请号：US18380954

申请日：2023-10-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Steven RAASCH ,  Andrew G. KEGEL

IPC: G06F12/1009 ,  G06F9/50 ,  G06F11/07 ,  G06F12/02 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1027 ,  G06F12/123

CPC classification number: G06F12/1009 ,  G06F9/5016 ,  G06F11/0772 ,  G06F12/0246 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1027 ,  G06F12/123

Abstract: A processing system includes a primary processor and a co-processor. The primary processor is couplable to a memory subsystem having at least one memory and operating to execute system software employing memory address translations based on one or more page tables stored in the memory subsystem. The co-processor is likewise couplable to the memory subsystem and operates to perform iterations of a page table walk through one or more page tables maintained for the memory subsystem and to perform one or more page management operations on behalf of the system software based the iterations of the page table walk. The page management operations performed by the co-processor include analytic data aggregation, free list management and page allocation, page migration management, page table error detection, and the like.

公开(公告)号：US20210342285A1

公开(公告)日：2021-11-04

申请号：US16863149

申请日：2020-04-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SeyedMohammad SEYEDZADEHDELCHEH ,  Steven RAASCH ,  Sergey BLAGODUROV

IPC: G06F13/40 ,  H03M7/30 ,  G06F13/42

Abstract: Data are serially communicated over an interconnect between an encoder and a decoder. The encoder includes a first training unit to count a frequency of symbol values in symbol blocks of a set of N number of symbol blocks in an epoch. A circular shift unit of the encoder stores a set of most-recently-used (MRU) amplitude values. An XOR unit is coupled to the first training unit and the first circular shift unit as inputs and to the interconnect as output. A transmitter is coupled to the encoder XOR unit and the interconnect and thereby contemporaneously sends symbols and trains on the symbols. In a system, a device includes a receiver and decoder that receive, from the encoder, symbols over the interconnect. The decoder includes its own training unit for decoding the transmitted symbols.