公开(公告)号：US09411542B2

公开(公告)日：2016-08-09

申请号：US14187058

申请日：2014-02-21

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Gregory M. Yukna

IPC: G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/061 ,  G06F3/0637 ,  G06F13/1668 ,  Y02D10/14

Abstract: In one example, there is disclosed herein a processor configured for interruptible atomic exclusive memory operations. For example, a load exclusive (LDEX) may be followed by a store exclusive (STREX), with the two together forming an atom. To facilitate timely handling of interrupts, the STREX operation is split into two parts. The STREX_INIT is not interruptible but has a determinate execution time because it takes a fixed number of clock cycles. The STREX_INIT sends the value out to the memory bus. It is followed by a STREX_SYNC operation that polls a flag for whether a return value is available. STREX_SYNC is interruptible, and methods are disclosed for determining whether, upon return from an interrupt, atomicity of the operation has been broken. If atomicity is broken, the instruction fails, while if atomicity is preserved, the instruction completes.

Abstract translation: 在一个示例中，本文公开了配置用于可中断原子排他存储器操作的处理器。 例如，负载独占（LDEX）可以后跟存储排他（STREX），两者一起形成一个原子。 为了方便及时处理中断，STREX操作分为两部分。 STREX_INIT不可中断，但具有确定的执行时间，因为它需要固定的时钟周期数。 STREX_INIT将值发送到内存总线。 之后是一个STREX_SYNC操作，轮询一个标志是否返回值可用。 STREX_SYNC是可中断的，并且公开了用于确定在从中断返回时是否已经破坏操作的原子性的方法。 如果原子性被破坏，则指令失败，而如果保留原子性，则指令完成。

公开(公告)号：US20150242334A1

公开(公告)日：2015-08-27

申请号：US14187058

申请日：2014-02-21

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Gregory M. Yukna

IPC: G06F12/14 ,  G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/061 ,  G06F3/0637 ,  G06F13/1668 ,  Y02D10/14

Abstract: In one example, there is disclosed herein a processor configured for interruptible atomic exclusive memory operations. For example, a load exclusive (LDEX) may be followed by a store exclusive (STREX), with the two together forming an atom. To facilitate timely handling of interrupts, the STREX operation is split into two parts. The STREX_INIT is not interruptible but has a determinate execution time because it takes a fixed number of clock cycles. The STREX_INIT sends the value out to the memory bus. It is followed by a STREX_SYNC operation that polls a flag for whether a return value is available. STREX_SYNC is interruptible, and methods are disclosed for determining whether, upon return from an interrupt, atomicity of the operation has been broken. If atomicity is broken, the instruction fails, while if atomicity is preserved, the instruction completes.

Abstract translation: 在一个示例中，本文公开了配置用于可中断原子排他存储器操作的处理器。 例如，负载独占（LDEX）可以后跟存储排他（STREX），两者一起形成一个原子。 为了方便及时处理中断，STREX操作分为两部分。 STREX_INIT不可中断，但具有确定的执行时间，因为它需要固定数量的时钟周期。 STREX_INIT将值发送到内存总线。 之后是一个STREX_SYNC操作，轮询一个标志是否返回值可用。 STREX_SYNC是可中断的，并且公开了用于确定在从中断返回时是否已经破坏操作的原子性的方法。 如果原子性被破坏，则指令失败，而如果保留原子性，则指令完成。