公开(公告)号：US09411542B2

公开(公告)日：2016-08-09

申请号：US14187058

申请日：2014-02-21

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Gregory M. Yukna

IPC: G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/061 ,  G06F3/0637 ,  G06F13/1668 ,  Y02D10/14

Abstract: In one example, there is disclosed herein a processor configured for interruptible atomic exclusive memory operations. For example, a load exclusive (LDEX) may be followed by a store exclusive (STREX), with the two together forming an atom. To facilitate timely handling of interrupts, the STREX operation is split into two parts. The STREX_INIT is not interruptible but has a determinate execution time because it takes a fixed number of clock cycles. The STREX_INIT sends the value out to the memory bus. It is followed by a STREX_SYNC operation that polls a flag for whether a return value is available. STREX_SYNC is interruptible, and methods are disclosed for determining whether, upon return from an interrupt, atomicity of the operation has been broken. If atomicity is broken, the instruction fails, while if atomicity is preserved, the instruction completes.

Abstract translation: 在一个示例中，本文公开了配置用于可中断原子排他存储器操作的处理器。 例如，负载独占（LDEX）可以后跟存储排他（STREX），两者一起形成一个原子。 为了方便及时处理中断，STREX操作分为两部分。 STREX_INIT不可中断，但具有确定的执行时间，因为它需要固定的时钟周期数。 STREX_INIT将值发送到内存总线。 之后是一个STREX_SYNC操作，轮询一个标志是否返回值可用。 STREX_SYNC是可中断的，并且公开了用于确定在从中断返回时是否已经破坏操作的原子性的方法。 如果原子性被破坏，则指令失败，而如果保留原子性，则指令完成。

公开(公告)号：US09092429B2

公开(公告)日：2015-07-28

申请号：US14040367

申请日：2013-09-27

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Michael S. Allen ,  John L. Redford

IPC: G06F3/06 ,  G06F13/28 ,  G06F13/38

CPC classification number: G06F13/28

Abstract: According to one example embodiment, a direct memory access (DMA) engine and buffer is disclosed. The vector buffer may be explicitly programmable, and may include advanced logic for reordering non-unity-stride vector data. An example MEMCPY instruction may provide an access request to the DMA buffer, which may then service the request asynchronously. Bitwise guards are set over memory in use, and cleared as each bit is read.

Abstract translation: 根据一个示例实施例，公开了直接存储器存取（DMA）引擎和缓冲器。 向量缓冲器可以是可显式可编程的，并且可以包括用于重新排序非单位步幅矢量数据的高级逻辑。 示例MEMCPY指令可以向DMA缓冲器提供访问请求，其可以异步地服务请求。 按位保护设置在使用中的内存中，并在读取每个位时清零。

公开(公告)号：US20140115302A1

公开(公告)日：2014-04-24

申请号：US13963793

申请日：2013-08-09

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Boris Lemer ,  Kaushal Sanghai ,  Michael G. Perkins ,  John L. Redford ,  Michael S. Allen

IPC: G06F9/30

CPC classification number: G06F9/30072 ,  G06F9/30101 ,  G06F9/325 ,  G06F9/3887

Abstract: According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.

Abstract translation: 根据示例性实施例，诸如数字信号处理器（DSP）的处理器被提供有用作谓词计数器的寄存器。 谓词计数器可以包括两个有用的值，并且除了用作执行指令的条件之外，还可以跟踪循环或条件分支内的嵌套级别。 在某些情况下，谓词计数器可以被配置为在单指令，多数据（SIMD）模式或SIMD-在寄存器（SWAR）模式下操作。

公开(公告)号：US09342306B2

公开(公告)日：2016-05-17

申请号：US13963793

申请日：2013-08-09

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Boris Lerner ,  Kaushal Sanghai ,  Michael G. Perkins ,  John L. Redford ,  Michael S. Allen

IPC: G06F9/44 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30072 ,  G06F9/30101 ,  G06F9/325 ,  G06F9/3887

Abstract: According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.

Abstract translation: 根据示例性实施例，诸如数字信号处理器（DSP）的处理器被提供有用作谓词计数器的寄存器。 谓词计数器可以包括两个有用的值，并且除了用作执行指令的条件之外，还可以跟踪循环或条件分支中的嵌套级别。 在某些情况下，谓词计数器可以被配置为在单指令，多数据（SIMD）模式或SIMD-在寄存器（SWAR）模式下操作。

公开(公告)号：US20150242334A1

公开(公告)日：2015-08-27

申请号：US14187058

申请日：2014-02-21

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Gregory M. Yukna

IPC: G06F12/14 ,  G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/061 ,  G06F3/0637 ,  G06F13/1668 ,  Y02D10/14

Abstract: In one example, there is disclosed herein a processor configured for interruptible atomic exclusive memory operations. For example, a load exclusive (LDEX) may be followed by a store exclusive (STREX), with the two together forming an atom. To facilitate timely handling of interrupts, the STREX operation is split into two parts. The STREX_INIT is not interruptible but has a determinate execution time because it takes a fixed number of clock cycles. The STREX_INIT sends the value out to the memory bus. It is followed by a STREX_SYNC operation that polls a flag for whether a return value is available. STREX_SYNC is interruptible, and methods are disclosed for determining whether, upon return from an interrupt, atomicity of the operation has been broken. If atomicity is broken, the instruction fails, while if atomicity is preserved, the instruction completes.

Abstract translation: 在一个示例中，本文公开了配置用于可中断原子排他存储器操作的处理器。 例如，负载独占（LDEX）可以后跟存储排他（STREX），两者一起形成一个原子。 为了方便及时处理中断，STREX操作分为两部分。 STREX_INIT不可中断，但具有确定的执行时间，因为它需要固定数量的时钟周期。 STREX_INIT将值发送到内存总线。 之后是一个STREX_SYNC操作，轮询一个标志是否返回值可用。 STREX_SYNC是可中断的，并且公开了用于确定在从中断返回时是否已经破坏操作的原子性的方法。 如果原子性被破坏，则指令失败，而如果保留原子性，则指令完成。

公开(公告)号：US20140115195A1

公开(公告)日：2014-04-24

申请号：US14040367

申请日：2013-09-27

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Michael S. Allen ,  John L. Redford

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: According to one example embodiment, a direct memory access (DMA) engine and buffer is disclosed. The vector buffer may be explicitly programmable, and may include advanced logic for reordering non-unity-stride vector data. An example MEMCPY instruction may provide an access request to the DMA buffer, which may then service the request asynchronously. Bitwise guards are set over memory in use, and cleared as each bit is read.

Abstract translation: 根据一个示例实施例，公开了直接存储器存取（DMA）引擎和缓冲器。 向量缓冲器可以是可显式可编程的，并且可以包括用于重新排序非单位步幅矢量数据的高级逻辑。 示例MEMCPY指令可以向DMA缓冲器提供访问请求，其可以异步地服务请求。 按位保护设置在使用中的内存中，并在读取每个位时清零。