公开(公告)号：US11688437B2

公开(公告)日：2023-06-27

申请号：US17481867

申请日：2021-09-22

Applicant: Apple Inc.

Inventor： Michael A. Dreesen ,  Shawn Searles ,  Jaemyung Lim ,  Jacek R. Wiatrowski

IPC: G11C7/06 ,  G11C7/08

CPC classification number: G11C7/08 ,  G11C7/065

Abstract: An amplifier system includes a differential amplifier and a calibration circuit. In response to a calibration operation, the calibration circuit generates a calibration value based on a test output signal generated by the differential amplifier circuit using a test input signal. The calibration value may be used to adjust loading of internal nodes of the differential amplifier circuit to compensate for imbalance in the differential amplifier circuit resulting from variation in manufacturing. By compensating for the imbalance, the offset of the differential amplifier may be reduced, allowing resolution of smaller differential voltages, thereby improving the performance of circuits employing the differential amplifier circuit.

公开(公告)号：US20220101892A1

公开(公告)日：2022-03-31

申请号：US17481867

申请日：2021-09-22

Applicant: Apple Inc.

Inventor： Michael A. Dreesen ,  Shawn Searles ,  Jaemyung Lim ,  Jacek R. Wiatrowski

IPC: G11C7/08 ,  G11C7/06

Abstract: An amplifier system includes a differential amplifier and a calibration circuit. In response to a calibration operation, the calibration circuit generates a calibration value based on a test output signal generated by the differential amplifier circuit using a test input signal. The calibration value may be used to adjust loading of internal nodes of the differential amplifier circuit to compensate for imbalance in the differential amplifier circuit resulting from variation in manufacturing. By compensating for the imbalance, the offset of the differential amplifier may be reduced, allowing resolution of smaller differential voltages, thereby improving the performance of circuits employing the differential amplifier circuit.

公开(公告)号：US20240063795A1

公开(公告)日：2024-02-22

申请号：US18108624

申请日：2023-02-12

Applicant: APPLE INC.

Inventor： Andrew Russell ,  Michael A. Dreesen ,  Adam Johnson ,  Jacek R. Wiatrowski

IPC: H03K19/003 ,  G01R31/3177

CPC classification number: H03K19/00315 ,  G01R31/3177

Abstract: An electronic circuit for dynamic evaluation of logic functions includes a discharging circuit, a first keeper circuit, a delay circuit and a second keeper circuit. The discharging circuit is configured to discharge an evaluation node. The first keeper circuit is configured to charge the evaluation node and configured to be disabled responsively to a first keeper control indication. The delay circuit is configured to generate a second keeper control indication that is delayed relative to the first keeper control indication. The second keeper circuit is configured to retain a charge on the evaluation node responsively to the second keeper control indication.