-
公开(公告)号：US11755050B2
公开(公告)日：2023-09-12
申请号：US17467910
申请日：2021-09-07
Applicant: Apple Inc.
Inventor： Mohammad Kazemi , Michael A. Dreesen
IPC: G05F3/26 , G11C11/417 , G11C5/14
CPC classification number: G05F3/262 , G11C5/147 , G11C11/417
Abstract: An adaptive current mirror circuit for current shaping with temperature is disclosed. The adaptive current mirror includes a current generator circuit configured to receive and input current and generate an output current using the input current and an overdrive voltage. The adaptive current mirror further includes a compensation circuit configured to adjust a value of the overdrive voltage based on temperature.
-
公开(公告)号：US20220101892A1
公开(公告)日：2022-03-31
申请号：US17481867
申请日：2021-09-22
Applicant: Apple Inc.
Inventor： Michael A. Dreesen , Shawn Searles , Jaemyung Lim , Jacek R. Wiatrowski
Abstract: An amplifier system includes a differential amplifier and a calibration circuit. In response to a calibration operation, the calibration circuit generates a calibration value based on a test output signal generated by the differential amplifier circuit using a test input signal. The calibration value may be used to adjust loading of internal nodes of the differential amplifier circuit to compensate for imbalance in the differential amplifier circuit resulting from variation in manufacturing. By compensating for the imbalance, the offset of the differential amplifier may be reduced, allowing resolution of smaller differential voltages, thereby improving the performance of circuits employing the differential amplifier circuit.
-
公开(公告)号：US09792979B1
公开(公告)日：2017-10-17
申请号：US15365462
申请日：2016-11-30
Applicant: Apple Inc.
Inventor： Michael A. Dreesen
IPC: G11C7/12 , G11C11/417 , G11C11/412 , G11C5/14
CPC classification number: G11C11/417 , G11C5/147 , G11C7/04 , G11C7/12 , G11C11/412 , G11C11/413 , G11C2029/5006
Abstract: Systems, apparatuses, and methods for tracking a retention voltage are disclosed. In one embodiment, a circuit is utilized for generating a standby voltage for a static random-access memory (SRAM) array. The circuit tracks the leakage current of the bitcells of the SRAM array as the leakage current varies over temperature. The circuit mirrors this leakage current and tracks the higher threshold voltage of a p-channel transistor or an n-channel transistor, with the p-channel and n-channel transistors matching the transistors in the bitcells of the SRAM array. The circuit includes a voltage regulator to supply power to the SRAM array at a supply voltage proportional to the higher threshold voltage tracked. Setting a supply voltage of the SRAM array based on threshold voltages and leakage current may reduce power consumption as compared to using a supply voltage based on a worst case operating conditions assumption for the SRAM array.
-
公开(公告)号：US10812081B1
公开(公告)日：2020-10-20
申请号：US16585304
申请日：2019-09-27
Applicant: Apple Inc.
Inventor： Michael R. Seningen , Michael A. Dreesen
IPC: H03K19/0185
Abstract: A computer system may include circuit blocks that may operate in different operating modes. When operating in a retention mode, a voltage level of a local power supply node for a particular circuit block may be less than a voltage level of the local power supply node when the particular circuit block is operating in an active mode. An output buffer circuit may be configured to generate, when the particular circuit block is operating in retention mode, an output signal using a circuit signal generated by the particular circuit block, and a voltage level corresponding to the active mode of operation.
-
公开(公告)号：US20180181193A1
公开(公告)日：2018-06-28
申请号：US15389332
申请日：2016-12-22
Applicant: Apple Inc.
Inventor： Amrinder S. Barn , Bo Zhao , Michael A. Dreesen
IPC: G06F1/32 , H03K19/0175 , H03K3/356 , G11C7/10
CPC classification number: H03K3/356104 , G11C7/106 , G11C29/32 , G11C2029/3202 , H03K3/356121 , H03K19/017509
Abstract: In an embodiment, an apparatus includes a first latch including a true storage node and a complement storage node, a discharge circuit, and a second latch. The first latch may pre-charge the true storage node and the complement storage node to a first voltage level using a clock signal. The discharge circuit may, in response to a determination that a scan mode signal is asserted, selectively discharge either the true storage node or the complement storage node based on a value of a scan data signal, and otherwise may selectively discharge either the true storage node or the complement storage node based on a value of a data signal. The second latch may store a value of a data bit based on a voltage level of the true storage node and a voltage level of the complement storage node.
-
Patent Agency Ranking
公开(公告)号：US20240063795A1
公开(公告)日：2024-02-22
申请号：US18108624
申请日：2023-02-12
Applicant: APPLE INC.
Inventor： Andrew Russell , Michael A. Dreesen , Adam Johnson , Jacek R. Wiatrowski
IPC: H03K19/003 , G01R31/3177
CPC classification number: H03K19/00315 , G01R31/3177
Abstract: An electronic circuit for dynamic evaluation of logic functions includes a discharging circuit, a first keeper circuit, a delay circuit and a second keeper circuit. The discharging circuit is configured to discharge an evaluation node. The first keeper circuit is configured to charge the evaluation node and configured to be disabled responsively to a first keeper control indication. The delay circuit is configured to generate a second keeper control indication that is delayed relative to the first keeper control indication. The second keeper circuit is configured to retain a charge on the evaluation node responsively to the second keeper control indication.
-
公开(公告)号：US20160240266A1
公开(公告)日：2016-08-18
申请号：US14621527
申请日：2015-02-13
Applicant: Apple Inc.
Inventor： Michael R. Seningen , Michael A. Dreesen , Edward M. McCombs
CPC classification number: G11C29/04 , G11C5/147 , G11C7/00 , G11C11/417 , G11C29/12005 , G11C29/50 , G11C2029/5002 , G11C2029/5602
Abstract: Methods and apparatuses for performing a disturb test on a memory are disclosed. Circuitry may be configured to store test data into one or more data storage cells. A regulation circuit may adjust a level of a power supply coupled to the one or more data storage cells from a first level to a second level. Once the voltage level of the power supply has reached the second level, the circuitry may perform a read operation on the one or more data storage cells. Upon completion of the read operation, the regulation circuit may return the voltage level of the power supply to the first level, and the circuitry may perform another read operation, the results of which, the circuitry may compare to the test data.
Abstract translation: 公开了对存储器进行干扰测试的方法和装置。 电路可以被配置为将测试数据存储到一个或多个数据存储单元中。 调节电路可以将耦合到一个或多个数据存储单元的电源的电平从第一电平调整到第二电平。 一旦电源的电压电平达到第二电平，电路就可以对一个或多个数据存储单元执行读取操作。 在读取操作完成时，调节电路可以将电源的电压电平恢复到第一电平，并且电路可以执行另一读取操作，其结果可以与测试数据进行比较。
-
公开(公告)号：US09412469B1
公开(公告)日：2016-08-09
申请号：US14621527
申请日：2015-02-13
Applicant: Apple Inc.
Inventor： Michael R. Seningen , Michael A. Dreesen , Edward M. McCombs
CPC classification number: G11C29/04 , G11C5/147 , G11C7/00 , G11C11/417 , G11C29/12005 , G11C29/50 , G11C2029/5002 , G11C2029/5602
Abstract: Methods and apparatuses for performing a disturb test on a memory are disclosed. Circuitry may be configured to store test data into one or more data storage cells. A regulation circuit may adjust a level of a power supply coupled to the one or more data storage cells from a first level to a second level. Once the voltage level of the power supply has reached the second level, the circuitry may perform a read operation on the one or more data storage cells. Upon completion of the read operation, the regulation circuit may return the voltage level of the power supply to the first level, and the circuitry may perform another read operation, the results of which, the circuitry may compare to the test data.
Abstract translation: 公开了对存储器进行干扰测试的方法和装置。 电路可以被配置为将测试数据存储到一个或多个数据存储单元中。 调节电路可以将耦合到一个或多个数据存储单元的电源的电平从第一电平调整到第二电平。 一旦电源的电压电平达到第二电平，电路就可以对一个或多个数据存储单元执行读取操作。 在读取操作完成时，调节电路可以将电源的电压电平恢复到第一电平，并且电路可以执行另一读取操作，其结果可以与测试数据进行比较。
-
公开(公告)号：US11688437B2
公开(公告)日：2023-06-27
申请号：US17481867
申请日：2021-09-22
Applicant: Apple Inc.
Inventor： Michael A. Dreesen , Shawn Searles , Jaemyung Lim , Jacek R. Wiatrowski
Abstract: An amplifier system includes a differential amplifier and a calibration circuit. In response to a calibration operation, the calibration circuit generates a calibration value based on a test output signal generated by the differential amplifier circuit using a test input signal. The calibration value may be used to adjust loading of internal nodes of the differential amplifier circuit to compensate for imbalance in the differential amplifier circuit resulting from variation in manufacturing. By compensating for the imbalance, the offset of the differential amplifier may be reduced, allowing resolution of smaller differential voltages, thereby improving the performance of circuits employing the differential amplifier circuit.
-
公开(公告)号：US20230074425A1
公开(公告)日：2023-03-09
申请号：US17467910
申请日：2021-09-07
Applicant: Apple Inc.
Inventor： Mohammad Kazemi , Michael A. Dreesen
IPC: G05F3/26 , G11C11/417
Abstract: An adaptive current mirror circuit for current shaping with temperature is disclosed. The adaptive current mirror includes a current generator circuit configured to receive and input current and generate an output current using the input current and an overdrive voltage. The adaptive current mirror further includes a compensation circuit configured to adjust a value of the overdrive voltage based on temperature.
-
-
-
-
-
-
-
-
-
Search Results
13
records
(took 0.018 seconds)
