公开(公告)号：US20180046460A1

公开(公告)日：2018-02-15

申请号：US15236769

申请日：2016-08-15

Applicant: ARM LIMITED

Inventor： Gary Alan GORMAN ,  Lee Evan EISEN ,  Neil BURGESS ,  Daniel ARULRAJ

IPC: G06F9/30

Abstract: Data processing apparatus comprises: processing circuitry to selectively apply vector processing operations to one or more data items of one or more data vectors each comprising a plurality of data items at respective vector positions in the data vector, according to the state of respective predicate indicators associated with the vector positions; a predicate store; and predicate generation circuitry to apply a processing operation to generate a set of predicate indicators, each associated with a respective one of the vector positions, to generate a count value indicative of the number of predicate indicators in the set having a given state, and to store the generated set of predicate indicators and the count value in the predicate store.

公开(公告)号：US20180046459A1

公开(公告)日：2018-02-15

申请号：US15236728

申请日：2016-08-15

Applicant: ARM LIMITED

Inventor： Neil BURGESS ,  Lee Evan EISEN ,  Gary Alan GORMAN ,  Daniel ARULRAJ

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30072 ,  G06F9/3013

Abstract: Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of one or more data vectors each comprising an ordered plurality of data items at respective vector positions in the data vector, according to the state of respective predicate indicators associated with the vector positions; predicate generation circuitry to apply a processing operation to generate an ordered set of predicate indicators, each associated with a respective one of the vector positions, the ordered set of predicate indicators being associated with an ordered set of active indicators each having an active or an inactive state; and a detector to detect a status flag indicative of whether a predicate indicator at a position, in the ordered set of predicate indicators, corresponding to the position of an outermost active indicator having the active state, has a given state; in which the detector comprises: first and second circuitry to combine the ordered set of predicate indicators and the ordered set of active indicators using first and second respective logical bit-wise combinations to generate first and second ordered sets of intermediate data; and arithmetic circuitry to combine the first and second ordered sets of intermediate data using an arithmetic combination generating a carry bit, the detector generating the status flag in dependence upon the carry bit.