公开(公告)号：US20190213009A1

公开(公告)日：2019-07-11

申请号：US15862728

申请日：2018-01-05

Applicant: Arm Limited

Inventor： Neil BURGESS ,  Lee Evan EISEN

IPC: G06F9/30 ,  G06F12/02 ,  G06F9/38

CPC classification number: G06F9/30098 ,  G06F9/30003 ,  G06F9/3826 ,  G06F9/3842 ,  G06F12/02

Abstract: An in-order processor has a mapping storage element to store current register mapping information identifying, for each of two or more architectural register specifiers, which physical register specifies valid data for that architectural register specifier. At least one checkpoint storage element stores checkpoint register mapping corresponding to a checkpoint of previous architectural state. This enables checkpoints to be saved and restored simply by transferring mapping information between the mapping and checkpoint storage elements, rather than transferring the actual state data.

公开(公告)号：US20190088307A1

公开(公告)日：2019-03-21

申请号：US15711116

申请日：2017-09-21

Applicant: ARM LIMITED

Inventor： Neil BURGESS ,  Nigel John STEPHENS ,  Lee Evan EISEN ,  Jaime FERRAGUT MARTINEZ-VARA DE REY

IPC: G11C11/4094 ,  G11C11/56

CPC classification number: G11C11/4094 ,  G06F9/30 ,  G11C7/1006 ,  G11C11/5621 ,  G11C19/28 ,  G11C19/38

Abstract: Circuitry comprises: a set of bit processing circuitries to apply two or more successive instances of bitwise processing to an ordered bit array; each bit processing circuitry for a given bit position within the ordered bit array comprising: bit shifting circuitry to selectively apply a bit shift of a respective input bit to a next bit processing circuitry in a first direction relative to the ordered bit array, in response to an active state of a bit shift control signal, the bit shifting circuitry not applying the bit shift in response to an inactive state of the bit shift control signal; and bit shift control circuitry to selectively allow or inhibit a bit shifting operation in response to one or more inhibit control signals; in which: the bit shift control circuitry is configured to selectively propagate an output inhibit control signal, indicating that a bit shifting operation should be inhibited, as an inhibit control signal to bit processing circuitry applying a next instance of the bitwise processing at the given bit position, in dependence upon the bit shift control signal and the one or more inhibit control signals.

公开(公告)号：US20210042261A1

公开(公告)日：2021-02-11

申请号：US16531210

申请日：2019-08-05

Applicant: Arm Limited

Inventor： Jelena MILANOVIC ,  Lee Evan EISEN ,  Nigel John STEPHENS

IPC: G06F15/80 ,  G06F9/30

Abstract: Data processing apparatus comprises processing circuitry to apply processing operations to one or more data items of a linear array comprising a plurality, n, of data items at respective positions in the linear array, the processing circuitry being configured to access an array of n×n storage locations, where n is an integer greater than one, the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to an array access instruction, to control the instruction processing circuitry to access, as a linear array, a set of n storage locations arranged in an array direction selected, under control of the array access instruction, from a set of candidate array directions comprising at least a first array direction and a second array direction different to the first array direction.

公开(公告)号：US20200042464A1

公开(公告)日：2020-02-06

申请号：US16055240

申请日：2018-08-06

Applicant: Arm Limited

Inventor： Daniel ARULRAJ ,  Lee Evan EISEN ,  Graeme Peter BARNES

IPC: G06F12/14 ,  G06F9/30

Abstract: An apparatus and method are provided for comparing regions associated with first and second bounded pointers to determine whether the region defined for the second bounded pointer is a subset of the region defined for the first bounded pointer. Each bounded pointer has a pointer value and associated upper and lower limits identifying the memory region for that bounded pointer. The apparatus stores first and second bounded pointer representations, each representation comprising a pointer value having p bits, and identifying the upper and lower limits in a compressed form by identifying a lower limit mantissa of q bits, an upper limit mantissa of q bits and an exponent value e. A most significant p−q−e bits of the lower limit and the upper limit is derivable from the most significant p−q−e bits of the pointer value. Mapping circuitry is used to map the lower limit mantissas and upper limit mantissas of the first and second bounded pointer representations to a q+x bit address space comprising 2x regions of size 2n1, where n1 is the value of n determined when using the exponent value of the first bounded pointer representation. Mantissa extension circuitry extends the lower limit and upper limit mantissas for each bounded pointer representation to create extended lower limit and upper limit mantissas comprising q+x bits, where a most significant x bits of each extended limit mantissa are mapping bits identifying which region the associated limit mantissa is mapped to. The determination circuitry then determines whether the region for the second pointer is a subset of the region for the first bounded pointer by comparing the extended lower and upper limit mantissas.

公开(公告)号：US20180307491A1

公开(公告)日：2018-10-25

申请号：US15493492

申请日：2017-04-21

Applicant: ARM Limited

Inventor： Alejandro Rico CARRO ,  Lee Evan EISEN

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/30036 ,  G06F9/3016 ,  G06F9/3867

Abstract: A processing pipeline has at least one front end stage for issuing micro-operations for execution in response to program instructions, and an execute stage for performing data processing in response to the micro-operations. At least one predicate register stores at least one predicate value. In response to a predicated vector instruction for triggering execution of two or more lanes of processing, the at least one front end stage issues at least one micro-operation to control the execute stage to mask an effect of a lane of processing indicated as disabled by a target predicate value. One of the front end stages may perform an early predicate lookup of the target predicate value to vary in dependence on the early predicate lookup, which micro-operations are issued to the execute store for a predicated vector instruction.

公开(公告)号：US20180046460A1

公开(公告)日：2018-02-15

申请号：US15236769

申请日：2016-08-15

Applicant: ARM LIMITED

Inventor： Gary Alan GORMAN ,  Lee Evan EISEN ,  Neil BURGESS ,  Daniel ARULRAJ

IPC: G06F9/30

Abstract: Data processing apparatus comprises: processing circuitry to selectively apply vector processing operations to one or more data items of one or more data vectors each comprising a plurality of data items at respective vector positions in the data vector, according to the state of respective predicate indicators associated with the vector positions; a predicate store; and predicate generation circuitry to apply a processing operation to generate a set of predicate indicators, each associated with a respective one of the vector positions, to generate a count value indicative of the number of predicate indicators in the set having a given state, and to store the generated set of predicate indicators and the count value in the predicate store.

公开(公告)号：US20180046459A1

公开(公告)日：2018-02-15

申请号：US15236728

申请日：2016-08-15

Applicant: ARM LIMITED

Inventor： Neil BURGESS ,  Lee Evan EISEN ,  Gary Alan GORMAN ,  Daniel ARULRAJ

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30072 ,  G06F9/3013

Abstract: Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of one or more data vectors each comprising an ordered plurality of data items at respective vector positions in the data vector, according to the state of respective predicate indicators associated with the vector positions; predicate generation circuitry to apply a processing operation to generate an ordered set of predicate indicators, each associated with a respective one of the vector positions, the ordered set of predicate indicators being associated with an ordered set of active indicators each having an active or an inactive state; and a detector to detect a status flag indicative of whether a predicate indicator at a position, in the ordered set of predicate indicators, corresponding to the position of an outermost active indicator having the active state, has a given state; in which the detector comprises: first and second circuitry to combine the ordered set of predicate indicators and the ordered set of active indicators using first and second respective logical bit-wise combinations to generate first and second ordered sets of intermediate data; and arithmetic circuitry to combine the first and second ordered sets of intermediate data using an arithmetic combination generating a carry bit, the detector generating the status flag in dependence upon the carry bit.