公开(公告)号：US11036639B2

公开(公告)日：2021-06-15

申请号：US15864062

申请日：2018-01-08

Applicant: ARM Limited

Inventor： Ricardo Daniel Queiros Alves ,  Nikos Nikoleris ,  Shidhartha Das ,  Andreas Lars Sandberg

IPC: G06F12/00 ,  G06F12/0864 ,  G06F12/0862 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/0888

Abstract: A cache apparatus is provided comprising a data storage structure providing N cache ways that each store data as a plurality of cache blocks. The data storage structure is organised as a plurality of sets, where each set comprises a cache block from each way, and further the data storage structure comprises a first data array and a second data array, where at least the second data array is set associative. A set associative tag storage structure stores a tag value for each cache block, with that set associative tag storage structure being shared by the first and second data arrays. Control circuitry applies an access likelihood policy to determine, for each set, a subset of the cache blocks of that set to be stored within the first data array. Access circuitry is then responsive to an access request to perform a lookup operation within an identified set of the set associative tag storage structure overlapped with an access operation to access within the first data array the subset of the cache blocks for the identified set. In the event of a hit condition being detected that identifies a cache block present in the first data array, that access request is then processed using the cache block accessed within the first data array. If instead a hit condition is detected that identifies a cache block absent in the first data array, then a further access operation is performed to access the identified cache block within a selected way of the second data array. Such a cache structure provides a high performance and energy efficient mechanism for storing cached data.