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    Non-volatile memory-based compact mixed-signal multiply-accumulate engine
    1.
    发明授权
    Non-volatile memory-based compact mixed-signal multiply-accumulate engine 有权

    公开(公告)号：US11886987B2

    公开(公告)日：2024-01-30

    申请号：US16451205

    申请日：2019-06-25

    申请人： Arm Limited

    发明人： Shidhartha Das ,  Matthew Mattina ,  Glen Arnold Rosendale ,  Fernando Garcia Redondo

    IPC分类号： G06N3/065 ,  G06N3/04 ,  G06N3/08

    CPC分类号： G06N3/065 ,  G06N3/04 ,  G06N3/08

    摘要： A multiply-accumulate method and architecture are disclosed. The architecture includes a plurality of networks of non-volatile memory elements arranged in tiled columns. Logic digitally modulates the equivalent conductance of individual networks among the plurality of networks to map the equivalent conductance of each individual network to a single weight within the neural network. A first partial selection of weights within the neural network is mapped into the equivalent conductances of the networks in the columns to enable the computation of multiply-and-accumulate operations by mixed-signal computation. The logic updates the mappings to select a second partial selection of weights to compute additional multiply-and-accumulate operations and repeats the mapping and computation operations until all computations for the neural network are completed.

    Current Spike Mitigation Technique for Neural Networks
    3.
    发明公开
    Current Spike Mitigation Technique for Neural Networks 审中-公开

    公开(公告)号：US20230297432A1

    公开(公告)日：2023-09-21

    申请号：US17697706

    申请日：2022-03-17

    申请人： Arm Limited

    发明人： Paul Nicholas Whatmough ,  Shidhartha Das

    IPC分类号： G06F9/50 ,  G06N3/02

    CPC分类号： G06F9/505 ,  G06N3/02

    摘要： Various implementations described herein are related to a method that monitors workloads of a neural network for current spikes. The method may determine current transitions of the workloads that result in rapid changes in load current consumption of the neural network. The method may modify load scheduling of the neural network so as to smooth and/or stabilize the current transitions of the workloads.

    Neural Network Architecture
    4.
    发明申请
    Neural Network Architecture 有权

    公开(公告)号：US20210365764A1

    公开(公告)日：2021-11-25

    申请号：US16879587

    申请日：2020-05-20

    申请人： Arm Limited

    发明人： Mbou Eyole ,  Shidhartha Das ,  Femando Garcia Redondo

    IPC分类号： G06N3/063 ,  G06N3/04

    摘要： Various implementations are related to an apparatus with memory cells arranged in columns and rows, and the memory cells are accessible with a column control voltage for accessing the memory cells via the columns and a row control voltage for accessing the memory cells via the rows. The apparatus may include neural network circuitry having neuronal junctions that are configured to receive, record, and provide information related to incoming voltage spikes associated with input signals based on resistance through the neuronal junctions. The apparatus may include stochastic re-programmer circuitry that receives the incoming voltage spikes, receives the information provided by the neuronal junctions, and reconfigure the information recorded in the neuronal junctions based on the incoming voltage spikes associated with the input signals along with a programming control signal provided by the memory circuitry.

    System-In-Package Architecture with Wireless Bus Interconnect
    5.
    发明申请
    System-In-Package Architecture with Wireless Bus Interconnect 有权

    公开(公告)号：US20210149834A1

    公开(公告)日：2021-05-20

    申请号：US16685090

    申请日：2019-11-15

    申请人： Arm Limited ,  ECS Partners Limited

    发明人： Benjamin James Fletcher ,  James Edward Myers ,  Shidhartha Das ,  Terrence Sui Tung Mak

    IPC分类号： G06F13/40 ,  H04L12/40

    摘要： A chip-carrier package includes a data processing system having one or more slave dies, a master die and a system bus. Each slave die includes a slave device and a slave-side wireless bus interface (WBI) coupled to the slave device. The master die includes a master device, one or more bus-side WBIs coupled to the master device. Each bus-side WBI is configured to be wirelessly coupled to at least one slave-side WBI of the one or more slave dies and a system bus. The system bus includes the one or more bus-side WBIs and the slave-side WBIs of the one or more slave-side dies. The system bus is configured to exchange information between the master device and the slave devices of the one or more slave dies.

    Dynamic Response of Power Delivery Network for Attestation and Identification
    6.
    发明申请
    Dynamic Response of Power Delivery Network for Attestation and Identification 有权

    公开(公告)号：US20210064789A1

    公开(公告)日：2021-03-04

    申请号：US17048521

    申请日：2019-04-18

    申请人： Arm Limited

    发明人： Hugo John Martin Vincent ,  Shidhartha Das ,  Milosch Meriac ,  Vasileios Tenentes

    IPC分类号： G06F21/75 ,  G06F21/44 ,  G06F1/28 ,  H04L9/08 ,  H04L9/00 ,  G01R19/165 ,  G01R31/08

    摘要： A method and authenticator for authenticating a device in a system using the electrical properties of the device is disclosed. Embodiments of the disclosure enable authentication by receiving a plurality of input seed values from a requestor. For each input seed value, load stimuli are generated to produce an electrical load sequence on a power delivery network powering at least part of the system. Noise induced in the power delivery network is measured in response to the electrical load sequence using one or more sensors located on the power delivery network. Based on the measured noise, a dynamic response property (magnitude and phase response as a function of frequency) of the power delivery network corresponding to a respective input seed value can be determined and returned to the requestor.

    Reconfigurable Circuit Architecture
    7.
    发明申请
    Reconfigurable Circuit Architecture 审中-公开

    公开(公告)号：US20200226095A1

    公开(公告)日：2020-07-16

    申请号：US16645993

    申请日：2018-09-25

    申请人： Arm Limited

    发明人： Mbou Eyole ,  Emre Ozer ,  Xabier Iturbe ,  Shidhartha Das

    IPC分类号： G06F15/78 ,  G11C14/00 ,  H03K19/17728

    摘要： A method of reconfiguration and a reconfigurable circuit architecture comprising a configurable volatile storage circuit and Non-Volatile Memory circuit elements; wherein the Non-Volatile memory circuit elements store multiple bit states for re-configuration, the multiple bit states being read from the Non-Volatile memory circuit elements and written into the configurable volatile storage circuit for reconfiguration. The Non-Volatile Memory circuit elements and the configurable volatile storage circuit are provided on a common die.

    Integrated circuit device, system and method
    10.
    发明授权
    Integrated circuit device, system and method 有权

    公开(公告)号：US12124384B2

    公开(公告)日：2024-10-22

    申请号：US17817686

    申请日：2022-08-05

    申请人： Arm Limited

    发明人： James Edward Myers ,  Shidhartha Das

    IPC分类号： G06F21/72 ,  G01R31/28 ,  G01R31/303 ,  G06F12/14 ,  G06F21/60 ,  G11C29/12 ,  H01L21/66

    CPC分类号： G06F12/1408 ,  G06F21/72 ,  G06F2212/1052

    摘要： An integrated circuit device including processing circuitry, communications circuitry configured to provide a communication link with a communication apparatus external to the integrated circuit device, and a memory accessible by the processing circuitry and by the communications circuitry, the memory comprising a memory region to which the processing circuitry has write access and to which the communications circuitry has read access, in which the processing circuitry is configured to write information to the memory region indicative of one or more use conditions of the integrated circuit device, and in which the communications circuitry is configured to access the memory region and to provide the information indicative of the one or more use conditions of the integrated circuit device via the communication link.