公开(公告)号：US20250004494A1

公开(公告)日：2025-01-02

申请号：US18345985

申请日：2023-06-30

Applicant: ATI Technologies ULC

Inventor： Carlos Javier Moreira ,  Michael McLean ,  Philip Ng

IPC: G06F1/04

Abstract: The disclosed device includes an input/output (I/O) system clock configured to operate at one of a plurality of clock states and a control circuit configured to dynamically adjust a clock state of the I/O system clock. The control circuit can update an activity level of a current clock state based at least on I/O traffic activity and, in response to the activity level going beyond an activity range for the current clock state, transition the I/O system clock to a neighboring clock state. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11307904B2

公开(公告)日：2022-04-19

申请号：US16224378

申请日：2018-12-18

Applicant: ATI TECHNOLOGIES ULC

Inventor： Michael McLean ,  Philip Ng

IPC: G06F9/50 ,  G06F9/4401 ,  G06F15/78

Abstract: A system-on-chip (SOC), includes a memory, a partition access module coupled to the memory, a partition requesting unit coupled to the partition access module, and a first input-output (IO) device coupled to the partition access module. The partition access module creates a first partition of the SOC. The first partition includes a first portion of a first processor, the first IO device, and a first portion of the memory. Based upon a partition request, the partition access module repartitions the SOC to create a dynamic partition. The dynamic partition includes the first portion of the first processor, the first input-output (IO) device, the first portion of the memory, and a second IO device not included in the first partition.

公开(公告)号：US11296905B2

公开(公告)日：2022-04-05

申请号：US16219149

申请日：2018-12-13

Applicant: ATI TECHNOLOGIES ULC

Inventor： Michael McLean ,  Philip Ng

IPC: H04L12/40 ,  G06F13/40 ,  H04L45/745 ,  H04L45/00

Abstract: A Management Component Transport Protocol platform management subsystem includes an internal bridge, a first segment group, and a second segment group. The first segment group is coupled to the internal bridge. The second segment group is coupled to the internal bridge and the first segment group. The first segment group has a first plurality of Peripheral Component Interconnect Express (PCIe)-based buses. The second segment group has a second plurality of PCIe-based buses, wherein based on an identification (ID)-routed packet from the first segment group to the second segment group, the internal bridge routes the ID-routed packet to the second segment group.