公开(公告)号：US08060670B2

公开(公告)日：2011-11-15

申请号：US12717918

申请日：2010-03-04

申请人： I-Kang Yu ,  Charles C. Lee ,  Shimon Chen ,  Abraham C. Ma

发明人： I-Kang Yu ,  Charles C. Lee ,  Shimon Chen ,  Abraham C. Ma

IPC分类号： G06F12/02 ,  G06F13/36 ,  G06F3/00

CPC分类号： G06F13/1684 ,  G11C16/102 ,  G11C2216/30

摘要： Methods and systems for storing and accessing data in UAS based flash memory device are disclosed. UAS based flash memory device comprises a controller and a plurality of non-volatile memories (e.g., flash memory) it controls. Controller is configured for connecting to a UAS host via a physical layer (e.g., plug and wire based on USB 3.0) and for conducting data transfer operations via two sets of logical pipes. Controller further comprises a random-access-memory (RAM) buffer configured for enabling parallel and duplex data transfer operations through the sets of logical pipes. In addition, a Smart Storage Switch configured for connecting multiple non-volatile memory devices is included in the controller. Finally, a security module/engine/unit is provided for data security via user authentication data encryption/decryption of the device. Furthermore, the flash memory device includes an optical transceiver configured for optical connection to a host also configured with an optical transceiver.

摘要翻译： 公开了在基于UAS的闪存设备中存储和访问数据的方法和系统。 基于UAS的闪存设备包括控制器和它控制的多个非易失性存储器（例如闪存）。 控制器被配置为经由物理层（例如，基于USB 3.0的插头和线路）连接到UAS主机，并且用于经由两组逻辑管道进行数据传输操作。 控制器还包括随机存取存储器（RAM）缓冲器，其配置用于通过逻辑管道集合实现并行和双工数据传输操作。 此外，控制器中还包括配置用于连接多个非易失性存储设备的智能存储交换机。 最后，通过设备的用户认证数据加密/解密来提供用于数据安全的安全模块/引擎/单元。 此外，闪速存储器件包括被配置用于光学连接到也配置有光收发器的主机的光收发器。

公开(公告)号：US20110179219A1

公开(公告)日：2011-07-21

申请号：US13076369

申请日：2011-03-30

申请人： Abraham C. Ma ,  Charles C. Lee ,  I-Kang Yu ,  Shimon Chen

发明人： Abraham C. Ma ,  Charles C. Lee ,  I-Kang Yu ,  Shimon Chen

IPC分类号： G06F12/00

CPC分类号： G06F3/0664 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0688 ,  G06F11/1456 ,  G06F12/0246 ,  G06F2212/225 ,  G06F2212/7201 ,  G06F2212/7208 ,  G06F2212/7211

摘要： A hybrid storage device comprises both solid-state disk (SDD) and at least one hard disk drive (HDD). The hybrid storage device has at least two operational modes: concatenation and safe. According to one aspect, the total capacity of hybrid storage device is the sum of SSD and at least one HDD in a concatenation or big mode, while the total capacity is the capacity of the HDD in a safe mode. In one embodiment, HDD is configured for storing a copy of the SSD's contents in a reserved area. In another, SSD comprises more than one identical flash memory devices controlled by a RAID controller.

摘要翻译： 混合存储设备包括固态盘（SDD）和至少一个硬盘驱动器（HDD）。 混合存储设备具有至少两种操作模式：级联和安全。 根据一个方面，混合存储设备的总容量是SSD和连接或大模式中的至少一个HDD的总和，而总容量是HDD在安全模式下的容量。 在一个实施例中，HDD被配置为将SSD的内容的副本存储在保留区域中。 另一方面，SSD包括由RAID控制器控制的多于一个的相同闪存设备。

公开(公告)号：US20110145489A1

公开(公告)日：2011-06-16

申请号：US13032564

申请日：2011-02-22

申请人： I-Kang Yu ,  Charles C. Lee ,  Shimon Chen ,  Abraham C. Ma

发明人： I-Kang Yu ,  Charles C. Lee ,  Shimon Chen ,  Abraham C. Ma

IPC分类号： G06F12/00

CPC分类号： G06F3/0656 ,  G06F3/0613 ,  G06F3/068 ,  G06F3/0685 ,  G06F3/0688

摘要： A hybrid storage device comprises both solid-state disk (SDD) and at least one hard disk drive (HDD). The hybrid storage device has at least two operational modes: concatenation and safe. According to one aspect, the total capacity of hybrid storage device is the sum of SSD and at least one HDD in a concatenation or big mode, while the total capacity is the capacity of the HDD in a safe mode.

摘要翻译： 混合存储设备包括固态盘（SDD）和至少一个硬盘驱动器（HDD）。 混合存储设备具有至少两种操作模式：级联和安全。 根据一个方面，混合存储设备的总容量是SSD和连接或大模式中的至少一个HDD的总和，而总容量是HDD在安全模式下的容量。

公开(公告)号：US20100185808A1

公开(公告)日：2010-07-22

申请号：US12717918

申请日：2010-03-04

申请人： I-Kang Yu ,  Charles C. Lee ,  Shimon Chen ,  Abraham C. Ma

发明人： I-Kang Yu ,  Charles C. Lee ,  Shimon Chen ,  Abraham C. Ma

IPC分类号： G06F12/02 ,  G06F13/36 ,  G06F12/14 ,  G06F13/00

CPC分类号： G06F13/1684 ,  G11C16/102 ,  G11C2216/30

摘要： Methods and systems for storing and accessing data in UAS based flash memory device are disclosed. UAS based flash memory device comprises a controller and a plurality of non-volatile memories (e.g., flash memory) it controls. Controller is configured for connecting to a UAS host via a physical layer (e.g., plug and wire based on USB 3.0) and for conducting data transfer operations via two sets of logical pipes. Controller further comprises a random-access-memory (RAM) buffer configured for enabling parallel and duplex data transfer operations through the sets of logical pipes. In addition, a Smart Storage Switch configured for connecting multiple non-volatile memory devices is included in the controller. Finally, a security module/engine/unit is provided for data security via user authentication data encryption/decryption of the device. Furthermore, the flash memory device includes an optical transceiver configured for optical connection to a host also configured with an optical transceiver.

摘要翻译： 公开了在基于UAS的闪存设备中存储和访问数据的方法和系统。 基于UAS的闪存设备包括控制器和它控制的多个非易失性存储器（例如闪存）。 控制器被配置为经由物理层（例如，基于USB 3.0的插头和线路）连接到UAS主机，并且用于经由两组逻辑管道进行数据传输操作。 控制器还包括随机存取存储器（RAM）缓冲器，其配置用于通过逻辑管道集合实现并行和双工数据传输操作。 此外，控制器中还包括配置用于连接多个非易失性存储设备的智能存储交换机。 最后，通过设备的用户认证数据加密/解密来提供用于数据安全的安全模块/引擎/单元。 此外，闪速存储器件包括被配置用于光学连接到也配置有光收发器的主机的光收发器。

公开(公告)号：US07890846B2

公开(公告)日：2011-02-15

申请号：US11739613

申请日：2007-04-24

申请人： Charles C. Lee ,  I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： Charles C. Lee ,  I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： H03M13/00

CPC分类号： H03M13/1545 ,  G06F11/1068 ,  G06F11/1076 ,  H03M13/153 ,  H03M13/1535 ,  H03M13/6561

摘要： One embodiment of the present includes a electronic data storage card having a Reed Solomon (RS) decoder having a syndrome calculator block responsive to a page of information, the page being organized into a plurality of data sections and the overhead being organized into a plurality of overhead sections. The syndrome calculator generates a syndrome for each of the data sections. The decoder further includes a root finder block responsive to the calculated syndrome and for generating at least two roots, a polynomial calculator block responsive to the at least two roots and operative to generate at least one error address, identifying a location in the data wherein the error lies, and an error symbol values calculator block coupled to the root finder and the polynomial calculator block and for generating a second error address, identifying a second location in the data wherein the error(s) lie.

摘要翻译： 本发明的一个实施例包括具有Reed Solomon（RS）解码器的电子数据存储卡，该解码器具有响应于信息页的校正子计算器块，该页被组织成多个数据段，并且开销被组织成多个 架空部分。 综合征计算器为每个数据部分产生综合征。 解码器还包括响应于所计算的校正子并用于生成至少两个根的根取景器块，响应于至少两个根并且可操作地生成至少一个错误地址的多项式计算器块，识别数据中的位置，其中， 并且错误符号值计算器块耦合到根查找器和多项式计算器块，并用于产生第二错误地址，识别错误所在的数据中的第二位置。

公开(公告)号：US07702831B2

公开(公告)日：2010-04-20

申请号：US11466759

申请日：2006-08-23

申请人： Abraham C. Ma ,  Charles C. Lee ,  I-Kang Yu ,  Edward W. Lee ,  Ming-Shiang Shen

发明人： Abraham C. Ma ,  Charles C. Lee ,  I-Kang Yu ,  Edward W. Lee ,  Ming-Shiang Shen

IPC分类号： G06F13/12

CPC分类号： G06F12/0246 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06F21/79 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

摘要翻译： 电子数据闪存卡可由主机访问，并且包括连接到存储数据文件的闪存设备的处理单元，以及被激活以便与主计算机建立通信的输入 - 输出接口电路。 在一个实施例中，电子数据闪存卡使用USB输入/输出接口电路与主计算机进行通信。 闪速存储器控制器包括用于将由主计算机发送的逻辑地址转换成与闪存器件的扇区相关联的物理地址的索引。 该索引由参考来自各种查找表中的值和存储在闪存设备中的有效数据的仲裁逻辑控制。 闪存控制器还包括先进先出单元（FIFO），用于在后台进程中回收闪速存储器件的过时扇区，使得它们可用于重新编程。

公开(公告)号：US07873837B1

公开(公告)日：2011-01-18

申请号：US11685143

申请日：2007-03-12

申请人： Charles C. Lee ,  I-Kang Yu ,  Edward W. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： Charles C. Lee ,  I-Kang Yu ,  Edward W. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F21/00 ,  H04L9/00 ,  H04K1/00

CPC分类号： G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data flash card includes a random number generator that generates a random number stored in the card and a host system each time the card is accessed by the host system. The random number is used by the host system to encrypt a logical branch address, a user password, and user data that is written to and stored in a secure area of the card. The random number is encrypted using a key associated with the card, and the encrypted random number is stored by the card with the associated encrypted data. The random number is not stored in the host system. A new random number is generated each time the card is queried. In a read process the host system decrypts the encrypted random number using the key, then uses the random number to decrypt the associated encrypted data. Access to read/write processes are password protected.

摘要翻译： 电子数据闪存卡包括随机数生成器，其生成存储在卡中的随机数，以及每次主机系统访问卡时的主机系统。 主机系统使用随机数来加密逻辑分支地址，用户密码和写入并存储在卡的安全区域中的用户数据。 使用与该卡相关联的密钥对该随机数进行加密，并且加密随机数由卡与相关联的加密数据一起存储。 随机数不存储在主机系统中。 每次查询卡片时都会产生一个新的随机数字。 在读取过程中，主机系统使用密钥解密加密的随机数，然后使用随机数来解密相关联的加密数据。 对读/写进程的访问受密码保护。

公开(公告)号：US07702984B1

公开(公告)日：2010-04-20

申请号：US11626347

申请日：2007-01-23

申请人： Charles C. Lee ,  I-Kang Yu ,  Edward W. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： Charles C. Lee ,  I-Kang Yu ,  Edward W. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F11/00 ,  G11C29/00 ,  G11C16/04

CPC分类号： G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G07C9/00087 ,  G07C2009/00095 ,  H01R13/629

摘要： A high volume testing/formatting process is provided for Universal Serial Bus-based (USB-based) electronic data flash cards (USB devices) that meets the increasing demand for USB electronic data flash cards (USB devices). A test host is simultaneously coupled to the multiple USB devices (e.g., using a multi-port card reader or a probe fixture), a controller endpoint value is read from each of the USB devices and verified with a known good value, and then testing/formatting is performed on each of the USB devices by writing predetermined data into each USB device in a pipelined manner, then reading out and testing the predetermined data. In one embodiment, the test host implements a special a USB driver that blocks standard USB registration procedures upon detecting the plurality of USB devices. Control and/or boot code data are written onto the flash memory device (i.e., instead of being provided on a controller ROM).

摘要翻译： 为通用串行总线（USB）电子数据闪存卡（USB设备）提供了大容量测试/格式化过程，可满足USB电子数据闪存卡（USB设备）日益增长的需求。 测试主机同时耦合到多个USB设备（例如，使用多端口读卡器或探头夹具），从每个USB设备读取控制器端点值，并用已知的良好值进行验证，然后测试 通过以流水线方式将预定数据写入每个USB设备，然后读出并测试预定数据，在每个USB设备上执行/格式化。 在一个实施例中，测试主机实现了一种特殊的USB驱动器，其在检测到多个USB设备时阻止标准USB注册过程。 控制和/或引导代码数据被写入快闪存储器件（即，不是设置在控制器ROM上）。

公开(公告)号：US20090240865A1

公开(公告)日：2009-09-24

申请号：US12426189

申请日：2009-04-17

申请人： I-Kang Yu ,  Abraham C. Ma ,  Charles C. Lee

发明人： I-Kang Yu ,  Abraham C. Ma ,  Charles C. Lee

IPC分类号： G06F13/00 ,  G06F13/20

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

摘要翻译： 多媒体卡/安全数字（MMC / SD）单芯片闪存设备包含一个MMC / SD闪存微控制器和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。 来自主机MMC / SD总线的MMC / SD事务由MMC / SD闪存微控制器上的总线收发器读取。 响应于MMC / SD事务中的命令，激活在MMC / SD闪存单片机中的CPU上执行的各种例程。 MMC / SD闪存单片机中的闪存控制器将数据从总线收发器传输到闪存大容量存储块以进行存储。 不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。 在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

公开(公告)号：US20080228984A1

公开(公告)日：2008-09-18

申请号：US12128916

申请日：2008-05-29

申请人： I-Kang Yu ,  Abraham C. Ma ,  Charles C. Lee

发明人： I-Kang Yu ,  Abraham C. Ma ,  Charles C. Lee

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

摘要翻译： 多媒体卡/安全数字（MMC / SD）单芯片闪存设备包含一个MMC / SD闪存微控制器和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。 来自主机MMC / SD总线的MMC / SD事务由MMC / SD闪存微控制器上的总线收发器读取。 响应于MMC / SD事务中的命令，激活在MMC / SD闪存单片机中的CPU上执行的各种例程。 MMC / SD闪存单片机中的闪存控制器将数据从总线收发器传输到闪存大容量存储块以进行存储。 不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。 在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。