Dispatcher for improved-performance non-volatile memory store operations

    公开(公告)号:US12131032B1

    公开(公告)日:2024-10-29

    申请号:US17987899

    申请日:2022-11-16

    申请人: Apple Inc.

    IPC分类号: G06F3/06

    摘要: A System on Chip (SoC) includes a processor, a parity generation circuit, and a dispatcher circuit. The processor is configured to produce store instructions for storing data blocks in a Non-Volatile-Memory (NVM). The parity generation circuit is configured to calculate parity blocks over the data blocks in accordance with a redundant storage scheme, to send the parity blocks to the NVM, and to produce completion notifications with respect to the parity blocks. The dispatcher circuit is configured to dispatch the store instructions to the NVM. The processor is further configured to send one or more parity-barrier instructions that specify synchronization barriers over the store instructions and the parity, and the dispatcher circuit is configured to dispatch the store instructions to the NVM in compliance with the parity-barrier instructions and the completion notifications.

    METHOD AND DATA PROCESSING APPARATUS FOR RESTRUCTURING INPUT DATA TO BE STORED IN A MULTI-LEVEL NAND FLASH MEMORY

    公开(公告)号:US20240329851A1

    公开(公告)日:2024-10-03

    申请号:US18625941

    申请日:2024-04-03

    申请人: Hyperstone GmbH

    发明人: Sami ALSALAMIN

    IPC分类号: G06F3/06

    摘要: Provided is a method and a data processing apparatus for restructuring input data to be stored in a flash memory having a plurality of multi-level flash memory cells. The method comprises: based on a defined page structure according to which the input data is segmented into multiple logical input pages, restructuring the segmented input data to obtain corresponding output data being segmented into logical output pages, wherein each output page has one or more associated destination data pages for storing content of the output page therein; and outputting the segmented output data for storage to the flash memory in accordance with the associations between the output pages and their respective destination data pages. The restructuring comprises assigning to each output page a respective corresponding input page, and selecting the respective input page for assignment to the respective output page.

    Identifying Multiple Resources of a Storage Network for Data Retrieval

    公开(公告)号:US20240314087A1

    公开(公告)日:2024-09-19

    申请号:US18668356

    申请日:2024-05-20

    摘要: Methods and apparatus for identifying multiple resources of a storage network for data retrieval are disclosed. In various embodiments, a determination is made to retrieve an encoded data slice from the storage network. Based on configuration information for the storage network, one or more configurations are identified, including a current configuration. For the identified configurations, ranked scoring information relating to the encoded data slice is determined for a plurality of resources associated with the identified configurations. Based on the ranked scoring information, a resource is selected for each of the identified configurations. In addition, a retrieval likelihood level for the data slice is determined for each of the selected resources. Based on the likelihood levels for the selected resources, one or more of the selected resources are identified for encoded data slice retrieval and read slice requests are issued to the one or more selected resources.

    Data shaping to reduce memory wear in a multi-tenant database

    公开(公告)号:US12067249B2

    公开(公告)日:2024-08-20

    申请号:US16550031

    申请日:2019-08-23

    IPC分类号: G06F3/06

    摘要: A multi-tenant database may maintain a plurality of datasets on a memory device that is subject to degraded operation caused by a subset of possible state transitions within the device's memory cells. A storage engine may identify entropy characteristics of datasets, independently of other datasets hosted on the memory, and use the entropy to construct a symbol table that maps from data within the dataset to symbols that may be stored on the memory device with a minimized number of state transitions.

    Storage device and operation method thereof

    公开(公告)号:US12061796B2

    公开(公告)日:2024-08-13

    申请号:US17808773

    申请日:2022-06-24

    IPC分类号: G06F3/06 G11C11/56 G11C16/04

    摘要: A storage device includes a memory device including a first memory region, a second memory region, and a third memory region, the first memory region having a lowest bit-density relative to the second memory region and the third memory region, a second memory region having a medium bit-density relative to the first memory region and the third memory region, and a third memory region having a highest bit-density relative to the first memory region and the second memory region; and a controller configured to control the memory device The controller is configured to distribute data received from a host to the first to third memory regions based on attributes of the data, to determine a current state based on a data distribution amount for each of the first to third memory regions and a respective size of each of the first to third memory regions, and to perform an action of increasing or decreasing a size of the second memory region under the current state based on a reinforcement learning result for mitigating a reduction in lifespan of the third memory region.

    MAXIMUM ROW ACTIVE TIME ENFORCEMENT FOR MEMORY DEVICES

    公开(公告)号:US20240231635A1

    公开(公告)日:2024-07-11

    申请号:US18405998

    申请日:2024-01-05

    IPC分类号: G06F3/06 G06F21/56

    摘要: A system for providing maximum row active time enforcement for memory devices is disclosed. A host device issues an activate command to activate a memory bank of a plurality of memory banks of a memory. The memory device activates the memory bank and determines whether a precharge command to close the first memory bank has been issued by the host device within a maximum threshold amount of time since issuance of the activate command. If the system determines that the precharge command has been issued by the host device within the threshold, the memory device closes the memory bank via the host-issued precharge command. If, however, the system determines that the precharge command has not been issued by the host device within the threshold, the memory device internally issues a precharge command to close the memory bank to reduce potential data loss and other harmful effects to the memory device.