公开(公告)号：US20240354002A1

公开(公告)日：2024-10-24

申请号：US18761596

申请日：2024-07-02

Applicant: PURE STORAGE, INC.

Inventor： BRIAN GOLD ,  JOHN HAYES ,  ROBERT LEE

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/14

CPC classification number: G06F3/0607 ,  G06F3/0619 ,  G06F3/0638 ,  G06F3/0655 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1441 ,  G06F3/0683 ,  G06F2212/1032 ,  G06F2212/7209

Abstract: A method for updates in a storage system is provided. The method includes writing identifiers, associated with data to be stored, to storage units of the storage system and writing trim records indicative of identifiers that are allowed to not exist in the storage system to the storage units. The method includes determining whether stored data corresponding to records of identifiers is valid based on the records of the identifiers and the trim records.

公开(公告)号：US20240345737A1

公开(公告)日：2024-10-17

申请号：US18756181

申请日：2024-06-27

Applicant: Lodestar Licensing Group, LLC

Inventor： Joe M. Jeddeloh

IPC: G06F3/06 ,  G06F12/0866 ,  G06F12/0868 ,  G11C7/10

CPC classification number: G06F3/0611 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/068 ,  G06F3/0685 ,  G06F12/0866 ,  G06F12/0868 ,  G11C7/1072 ,  G06F2212/2022 ,  G06F2212/60

Abstract: Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed.

公开(公告)号：US12101379B2

公开(公告)日：2024-09-24

申请号：US18312435

申请日：2023-05-04

Applicant: PURE STORAGE, INC.

Inventor： Prabhath Sajeepa ,  Daniel Talayco ,  Qing Yang ,  Robert Lee

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/10 ,  G06F11/20 ,  G06F12/02 ,  G11C29/52 ,  H03M13/15 ,  H04L49/10 ,  H04L67/1097 ,  H04L67/51

CPC classification number: H04L67/1097 ,  G06F3/06 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0685 ,  G06F3/0688 ,  G06F3/0689 ,  G06F11/1068 ,  G06F11/2092 ,  G06F12/0246 ,  G11C29/52 ,  H03M13/154 ,  H04L49/10 ,  H04L67/51 ,  G06F11/108 ,  G06F2201/805 ,  G06F2201/845 ,  G06F2212/7206 ,  G06F2212/7207

Abstract: A storage system is provided. The storage system includes a first storage cluster, the first storage cluster having a first plurality of storage nodes coupled together and a second storage cluster, the second storage cluster having a second plurality of storage nodes coupled together. The system includes an interconnect coupling the first storage cluster and the second storage cluster and a first pathway coupling the interconnect to each storage cluster. The system includes a second pathway, the second pathway coupling at least one fabric module within a chassis to each blade within the chassis.

公开(公告)号：US12099731B2

公开(公告)日：2024-09-24

申请号：US18158989

申请日：2023-01-24

Applicant: VMware LLC

Inventor： Siddhartha Visveswara Jayanti ,  Marcos Kawazoe Aguilera ,  Naama Ben David

IPC: G06F12/00 ,  G06F3/06 ,  G06F16/22

CPC classification number: G06F3/0631 ,  G06F3/0611 ,  G06F3/0685 ,  G06F16/2246

Abstract: In one set of embodiments, a computer system can receive a request to insert or delete a key into or from a plurality of keys maintained by a dynamic search data structure, where the dynamic search data structure is implemented using a balanced binary search tree (BBST) comprising a plurality of nodes corresponding to the plurality of keys, where a first subset of the plurality of nodes are stored in the first memory tier, and where a second subset of the plurality of nodes are stored in the second memory tier. The computer system can further execute the request to insert or delete the key, where the executing results in a change in height of at least one node in the plurality of nodes. In response to the executing, the computer system can move one or more nodes in the plurality of nodes between the first and second memory tiers, the moving causing a threshold number of nodes of highest height in the BBST to be stored in the first memory tier.

公开(公告)号：US20240289021A1

公开(公告)日：2024-08-29

申请号：US18173229

申请日：2023-02-23

Applicant: International Business Machines Corporation

Inventor： Daniel WADDINGTON ,  Saransh GUPTA

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0653 ,  G06F3/0685

Abstract: Embodiments of the present disclosure provide an enhanced system and methods for optimizing data placement in a memory hierarchy. A disclosed non-limiting computer-implemented method configures a counter block comprising access frequency counters mapped into an application memory space, and configures a counter map, where each entry in the counter map associates an application-defined memory region with the access frequency counters of the counter block. A memory controller identifies a memory access in a given application-defined memory region and compares an access address with a mask in the counter map to track the memory access. The memory controller generates a heatmap representing a frequency count of accesses to quantized memory using the access frequency counters. Generating the heatmap is performed by memory controller hardware.

公开(公告)号：US20240248601A1

公开(公告)日：2024-07-25

申请号：US18623811

申请日：2024-04-01

Applicant: Lodestar Licensing Group LLC

Inventor： Robert M. Walker ,  James A. Hall, JR.

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0605 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/261 ,  G06F2212/7203 ,  G06F2212/7207

Abstract: The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can perform operations on a number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein the operations can read data from the number of block buffers and write data to the number of block buffers on the memory device.

公开(公告)号：US20240220112A1

公开(公告)日：2024-07-04

申请号：US18092007

申请日：2022-12-30

Applicant: SK Hynix NAND Product Solutions Corp. (dba Solidigm)

Inventor： Sarvesh Varakabe Gangadhar ,  Mark Anthony Golez ,  Jacky Le

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0685

Abstract: This application is directed to dynamic management of memory read request in a memory system of an electronic device. The electronic device identifies a queue of memory access requests to access the memory system. The queue of memory access requests including at least one host read request and a current system read request. The electronic device monitors a workload condition of the memory system based on the queue of memory access requests, and generates at least a first system read request and a second system read request from the current system read request based on the workload condition of the memory system. The queue of memory access requests is updated by inserting the at least one host read request after the first system read request and before the second system read request.

公开(公告)号：US12019895B2

公开(公告)日：2024-06-25

申请号：US18125625

申请日：2023-03-23

Applicant: Lodestar Licensing Group LLC

Inventor： Perry V. Lea ,  Glen E. Hush

IPC: G06F3/06 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0685 ,  G11C7/1006 ,  G11C7/1072 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2207/2236 ,  G11C2207/2245

Abstract: The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.

公开(公告)号：US12014058B2

公开(公告)日：2024-06-18

申请号：US18146996

申请日：2022-12-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Weiliang Jing ,  Zhengbo Wang ,  Jingjie Cui

IPC: G06F3/06 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0685 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063

Abstract: A stacked memory includes a volatile memory die and a non-volatile memory die that are stacked together. The non-volatile memory die includes a non-volatile storage array and a peripheral circuit. The peripheral circuit includes a power integrity circuit and a signal integrity circuit. The power integrity circuit is configured to perform power integrity optimization on a power supply obtained from a lower-layer die and then transmit the power supply to an upper-layer die. The signal integrity circuit is configured to perform signal integrity optimization on a signal obtained from a lower-layer die and then transmit the signal to an upper-layer die.

公开(公告)号：US20240195933A1

公开(公告)日：2024-06-13

申请号：US18065506

申请日：2022-12-13

Applicant: Jay Jason Bartlett

Inventor： Jay Jason Bartlett

IPC: H04N5/765 ,  G06F3/06 ,  G11B15/68 ,  H04N5/76 ,  H04N5/782 ,  H04N5/907 ,  H04N7/18

CPC classification number: H04N5/765 ,  G06F3/0608 ,  G06F3/0647 ,  G06F3/0685 ,  G11B15/6895 ,  H04N5/7605 ,  H04N5/782 ,  H04N5/907 ,  H04N7/181

Abstract: This invention relates to video surveillance management solutions. More specifically this invention relates to the integration of multiple tiers of dissimilar computer data storage technologies in such a manner to deliver longer term video retention and easy video playback. The device captures video data from multiple surveillance cameras and stores it on computer hard drive and then replicates to a second tier of digital data tape storage. Video retention policies are determined from parameters for the number of cameras, frame rates, resolution, and number of days of video retention desired. Storage procedures are set for multiple tiers of video storage that will allow for the highest quality video to be recorded without alteration or manipulation. A human video operator will then have the ability to select any available recorded video under management and have that video retrieved and available for display and playback without any additional steps or human interaction.