公开(公告)号：US20180024938A1

公开(公告)日：2018-01-25

申请号：US15216071

申请日：2016-07-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Timour T. Paltashev ,  Christopher Brennan

IPC: G06F12/1009 ,  G06F12/02 ,  G06F12/128

CPC classification number: G06F12/1009 ,  G06F12/023 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/128 ,  G06F2212/1044 ,  G06F2212/657

Abstract: A processing system for reduction of a virtual memory page fault rate that includes a first memory to store a dataset, a second memory to store a subset of the dataset, and a processing unit. The processing unit is configured to receive a memory access request including a virtual address and determine whether the virtual address is mapped to a first physical page in the first memory and or a second physical page in the second memory. The processing unit maps a third physical page in a free page pool of the second memory to the virtual address in response to the virtual address not being mapped to the second physical page. The processing unit also grants access to the third physical page that is mapped to the virtual address.