公开(公告)号：US20170371784A1

公开(公告)日：2017-12-28

申请号：US15192542

申请日：2016-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan R. Alsop ,  Bradford Beckmann

IPC: G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0808 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/0897

CPC classification number: G06F12/0897 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0891 ,  G06F2212/6042

Abstract: A processing system includes one or more first caches and one or more first lock tables associated with the one or more first caches. The processing system also includes one or more processing units that each include a plurality of compute units for concurrently executing work-groups of work items, a plurality of second caches associated with the plurality of compute units and configured in a hierarchy with the one or more first caches, and a plurality of second lock tables associated with the plurality of second caches. The first and second lock tables indicate locking states of addresses of cache lines in the corresponding first and second caches on a per-line basis.

公开(公告)号：US11042484B2

公开(公告)日：2021-06-22

申请号：US15192542

申请日：2016-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan R. Alsop ,  Bradford Beckmann

IPC: G06F12/0897 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0891

Abstract: A processing system includes one or more first caches and one or more first lock tables associated with the one or more first caches. The processing system also includes one or more processing units that each include a plurality of compute units for concurrently executing work-groups of work items, a plurality of second caches associated with the plurality of compute units and configured in a hierarchy with the one or more first caches, and a plurality of second lock tables associated with the plurality of second caches. The first and second lock tables indicate locking states of addresses of cache lines in the corresponding first and second caches on a per-line basis.