公开(公告)号：US20240111674A1

公开(公告)日：2024-04-04

申请号：US17955618

申请日：2022-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Alok Garg ,  Neil N Marketkar ,  Matthew T. Sobel

IPC: G06F12/0811 ,  G06F12/0875 ,  G06F12/0884

CPC classification number: G06F12/0811 ,  G06F12/0875 ,  G06F12/0884

Abstract: Data reuse cache techniques are described. In one example, a load instruction is generated by an execution unit of a processor unit. In response to the load instruction, data is loaded by a load-store unit for processing by the execution unit and is also stored to a data reuse cache communicatively coupled between the load-store unit and the execution unit. Upon receipt of a subsequent load instruction for the data from the execution unit, the data is loaded from the data reuse cache for processing by the execution unit.

公开(公告)号：US12066940B2

公开(公告)日：2024-08-20

申请号：US17955618

申请日：2022-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Alok Garg ,  Neil N Marketkar ,  Matthew T. Sobel

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0884

CPC classification number: G06F12/0811 ,  G06F12/0875 ,  G06F12/0884

Abstract: Data reuse cache techniques are described. In one example, a load instruction is generated by an execution unit of a processor unit. In response to the load instruction, data is loaded by a load-store unit for processing by the execution unit and is also stored to a data reuse cache communicatively coupled between the load-store unit and the execution unit. Upon receipt of a subsequent load instruction for the data from the execution unit, the data is loaded from the data reuse cache for processing by the execution unit.