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公开(公告)号：US20210096874A1
公开(公告)日：2021-04-01
申请号：US16586642
申请日：2019-09-27
发明人： Matthew T. Sobel , Joshua James Lindner , Neil N. Marketkar , Kai Troester , Emil Talpes , Ashok Tirupathy Venkatachar
IPC分类号： G06F9/38
摘要： Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.
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公开(公告)号：US20220027162A1
公开(公告)日：2022-01-27
申请号：US17497572
申请日：2021-10-08
发明人： Matthew T. Sobel , Joshua James Lindner , Neil N. Marketkar , Kai Troester , Emil Talpes , Ashok Tirupathy Venkatachar
IPC分类号： G06F9/38
摘要： Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.
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公开(公告)号：US11113056B2
公开(公告)日：2021-09-07
申请号：US16698808
申请日：2019-11-27
发明人： John M. King , Matthew T. Sobel
IPC分类号： G06F9/38 , G06F9/30 , G06F9/54 , G06F12/0811
摘要： A technique for performing store-to-load forwarding is provided. The technique includes determining a virtual address for data to be loaded for the load instruction, identifying a matching store instruction from one or more store instruction memories by comparing a virtual-address-based comparison value for the load instruction to one or more virtual-address-based comparison values of one or more store instructions, determining a physical address for the load instruction, and validating the load instruction based on a comparison between the physical address of the load instruction and a physical address of the matching store instruction.
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公开(公告)号：US12066940B2
公开(公告)日：2024-08-20
申请号：US17955618
申请日：2022-09-29
发明人： Alok Garg , Neil N Marketkar , Matthew T. Sobel
IPC分类号： G06F12/00 , G06F12/0811 , G06F12/0875 , G06F12/0884
CPC分类号： G06F12/0811 , G06F12/0875 , G06F12/0884
摘要： Data reuse cache techniques are described. In one example, a load instruction is generated by an execution unit of a processor unit. In response to the load instruction, data is loaded by a load-store unit for processing by the execution unit and is also stored to a data reuse cache communicatively coupled between the load-store unit and the execution unit. Upon receipt of a subsequent load instruction for the data from the execution unit, the data is loaded from the data reuse cache for processing by the execution unit.
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公开(公告)号：US11334384B2
公开(公告)日：2022-05-17
申请号：US16709527
申请日：2019-12-10
摘要： Systems, apparatuses, and methods for implementing scheduler queue assignment burst mode are disclosed. A scheduler queue assignment unit receives a dispatch packet with a plurality of operations from a decode unit in each clock cycle. The scheduler queue assignment unit determines if the number of operations in the dispatch packet for any class of operations is greater than a corresponding threshold for dispatching to the scheduler queues in a single cycle. If the number of operations for a given class is greater than the corresponding threshold, and if a burst mode counter is less than a burst mode window threshold, the scheduler queue assignment unit dispatches the extra number of operations for the given class in a single cycle. By operating in burst mode for a given operation class during a small number of cycles, processor throughput can be increased without starving the processor of other operation classes.
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公开(公告)号：US11294724B2
公开(公告)日：2022-04-05
申请号：US16585424
申请日：2019-09-27
摘要： An approach is provided for allocating a shared resource to threads in a multi-threaded microprocessor based upon the usefulness of the shared resource to each of the threads. The usefulness of a shared resource to a thread is determined based upon the number of entries in the shared resource that are allocated to the thread and the number of active entries that the thread has in the shared resource. Threads that are allocated a large number of entries in the shared resource and have a small number of active entries in the shared resource, indicative of a low level of parallelism, can operate efficiently with fewer entries in the shared resource, and have their allocation limit in the shared resource reduced.
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公开(公告)号：US11144324B2
公开(公告)日：2021-10-12
申请号：US16586642
申请日：2019-09-27
发明人： Matthew T. Sobel , Joshua James Lindner , Neil N. Marketkar , Kai Troester , Emil Talpes , Ashok Tirupathy Venkatachar
IPC分类号： G06F9/38
摘要： Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.
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公开(公告)号：US20210173702A1
公开(公告)日：2021-06-10
申请号：US16709527
申请日：2019-12-10
IPC分类号： G06F9/48
摘要： Systems, apparatuses, and methods for implementing scheduler queue assignment burst mode are disclosed. A scheduler queue assignment unit receives a dispatch packet with a plurality of operations from a decode unit in each clock cycle. The scheduler queue assignment unit determines if the number of operations in the dispatch packet for any class of operations is greater than a corresponding threshold for dispatching to the scheduler queues in a single cycle. If the number of operations for a given class is greater than the corresponding threshold, and if a burst mode counter is less than a burst mode window threshold, the scheduler queue assignment unit dispatches the extra number of operations for the given class in a single cycle. By operating in burst mode for a given operation class during a small number of cycles, processor throughput can be increased without starving the processor of other operation classes.
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公开(公告)号：US20210157590A1
公开(公告)日：2021-05-27
申请号：US16698808
申请日：2019-11-27
发明人： John M. King , Matthew T. Sobel
IPC分类号： G06F9/30 , G06F12/0811 , G06F9/54
摘要： A technique for performing store-to-load forwarding is provided. The technique includes determining a virtual address for data to be loaded for the load instruction, identifying a matching store instruction from one or more store instruction memories by comparing a virtual-address-based comparison value for the load instruction to one or more virtual-address-based comparison values of one or more store instructions, determining a physical address for the load instruction, and validating the load instruction based on a comparison between the physical address of the load instruction and a physical address of the matching store instruction.
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公开(公告)号：US09563573B2
公开(公告)日：2017-02-07
申请号：US13970735
申请日：2013-08-20
发明人： Matthew T. Sobel
CPC分类号： G06F12/121 , G11C7/12 , G11C11/419
摘要： A memory can be a sum addressed memory (SAM) that receives, for each read access, two address values (e.g. a base address and an offset) having a sum that indicates the entry of the memory to be read (the read entry). A decoder adds the two address value to identify the read entry. Concurrently, a predecode module predecodes the two address values to identify a set of entries (e.g. two different entries) at the memory, whereby the set includes the entry to be read. The predecode module generates a precharge disable signal to terminate precharging at the set of entries which includes the entry to be read. Because the precharge disable signal is based on predecoded address information, it can be generated without waiting for a full decode of the read address entry.
摘要翻译： 存储器可以是和寻址存储器（SAM），其针对每个读取访问接收具有指示要读取的存储器（读取条目）的条目的和的两个地址值（例如，基地址和偏移量）。 解码器将添加两个地址值以识别读取条目。 同时，预解码模块预先对两个地址值进行解码，以在存储器处标识一组条目（例如两个不同的条目），由此该集合包括要读取的条目。 预解码模块产生预充电禁止信号，以在包括要读取的条目的条目集合处终止预充电。 由于预充电禁止信号基于预解码的地址信息，所以可以在不等待读取地址条目的完全解码的情况下生成预充电禁止信号。
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