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公开(公告)号：US20090265508A1
公开(公告)日：2009-10-22
申请号：US12493500
申请日：2009-06-29
CPC分类号： G11C16/349 , G06F12/0246 , G06F2212/7205
摘要： A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated to perform memory system housekeeping operations in the foreground during execution of a host command, wherein the housekeeping operations are unrelated to execution of the host command. Both one or more such housekeeping operations and execution of the host command are performed within a time budget established for executing that particular command. One such command is to write data being received to the memory. One such housekeeping operation is to level out the wear of the individual blocks that accumulates through repetitive erasing and re-programming.
摘要翻译： 操作一个可重新编程的非易失性存储器系统，例如闪存EEPROM系统，其具有分组为可同时擦除的单元块的存储器单元，以在主机命令的执行期间在前台执行存储器系统管理操作，其中， 内务管理操作与主机命令的执行无关。 在为执行该特定命令建立的时间预算内执行一个或多个此类内务处理操作和主机命令的执行。 一个这样的命令是将正在接收的数据写入存储器。 一个这样的内务处理操作是通过重复擦除和重新编程来平衡累积的各个块的磨损。
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公开(公告)号：US07315917B2
公开(公告)日：2008-01-01
申请号：US11312985
申请日：2005-12-19
CPC分类号： G11C16/349 , G06F12/0246 , G06F2212/7205
摘要： A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated to perform memory system housekeeping operations in the foreground during execution of a host command, wherein the housekeeping operations are unrelated to execution of the host command. Both one or more such housekeeping operations and execution of the host command are performed within a time budget established for executing that particular command. One such command is to write data being received to the memory. One such housekeeping operation is to level out the wear of the individual blocks that accumulates through repetitive erasing and re-programming.
摘要翻译： 操作一个可重新编程的非易失性存储器系统，例如闪存EEPROM系统，其具有分组为可同时擦除的单元块的存储器单元，以在主机命令的执行期间在前台执行存储器系统管理操作，其中， 内务管理操作与主机命令的执行无关。 在为执行该特定命令建立的时间预算内执行一个或多个此类内务处理操作和主机命令的执行。 一个这样的命令是将正在接收的数据写入存储器。 一个这样的内务处理操作是通过重复擦除和重新编程来平衡累积的各个块的磨损。
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公开(公告)号：US07565478B2
公开(公告)日：2009-07-21
申请号：US11949618
申请日：2007-12-03
CPC分类号： G11C16/349 , G06F12/0246 , G06F2212/7205
摘要： A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated to perform memory system housekeeping operations in the foreground during execution of a host command, wherein the housekeeping operations are unrelated to execution of the host command. Both one or more such housekeeping operations and execution of the host command are performed within a time budget established for executing that particular command. One such command is to write data being received to the memory. One such housekeeping operation is to level out the wear of the individual blocks that accumulates through repetitive erasing and re-programming.
摘要翻译： 操作一个可重新编程的非易失性存储器系统，例如闪存EEPROM系统，其具有分组为可同时擦除的单元块的存储器单元，以在主机命令的执行期间在前台执行存储器系统管理操作，其中， 内务管理操作与主机命令的执行无关。 在为执行该特定命令建立的时间预算内执行一个或多个此类内务处理操作和主机命令的执行。 一个这样的命令是将正在接收的数据写入存储器。 一个这样的内务处理操作是通过重复擦除和重新编程来平衡累积的各个块的磨损。
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公开(公告)号：US08364883B2
公开(公告)日：2013-01-29
申请号：US12493500
申请日：2009-06-29
CPC分类号： G11C16/349 , G06F12/0246 , G06F2212/7205
摘要： A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated to perform memory system housekeeping operations in the foreground during execution of a host command, wherein the housekeeping operations are unrelated to execution of the host command. Both one or more such housekeeping operations and execution of the host command are performed within a time budget established for executing that particular command. One such command is to write data being received to the memory. One such housekeeping operation is to level out the wear of the individual blocks that accumulates through repetitive erasing and re-programming.
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5.发明授权公开(公告)号：US08700840B2
公开(公告)日：2014-04-15
申请号：US12348895
申请日：2009-01-05
申请人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
发明人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
CPC分类号： G06F12/0866 , G06F12/0246 , G06F12/0804 , G06F2212/7203 , G06F2212/7204 , G11C11/5628 , G11C2211/5641 , Y02D10/13
摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to archive data from the cache memory to the main memory depend on the attributes of the data to be archived, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.
摘要翻译： 将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。 缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。 在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。 将数据从高速缓冲存储器归档到主存储器的决定取决于要归档的数据的属性，主存储器部分中的块的状态和高速缓存部分中的块的状态。
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6.发明授权公开(公告)号：US08244960B2
公开(公告)日：2012-08-14
申请号：US12348899
申请日：2009-01-05
申请人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
发明人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F2212/224 , G06F2212/7203 , G06F2212/7204
摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache.
摘要翻译： 将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。 缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。 在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。 响应于增加容量的需求，高速缓冲存储器具有通过从主存储器分配块而动态增加的容量。 优选地，分配耐力计数高于平均值的块。 数据的逻辑地址被划分为区域以限制高速缓存的索引的大小。
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7.发明申请公开(公告)号：US20100174847A1
公开(公告)日：2010-07-08
申请号：US12348899
申请日：2009-01-05
申请人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
发明人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F2212/224 , G06F2212/7203 , G06F2212/7204
摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache.
摘要翻译： 将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。 缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。 在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。 响应于增加容量的需求，高速缓冲存储器具有通过从主存储器分配块而动态增加的容量。 优选地，分配耐力计数高于平均值的块。 数据的逻辑地址被划分为区域以限制高速缓存的索引的大小。
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公开(公告)号：US08094500B2
公开(公告)日：2012-01-10
申请号：US12348891
申请日：2009-01-05
申请人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
发明人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G06F12/0246 , G06F2212/7202 , G06F2212/7203 , G11C16/0483 , G11C29/00 , G11C29/76 , G11C29/808 , G11C2211/5641 , G11C2211/5643
摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to write data to the cache memory or directly to the main memory depend on the attributes and characteristics of the data to be written, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.
摘要翻译： 将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。 缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。 在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。 将数据写入高速缓冲存储器或直接写入主存储器的决定取决于要写入的数据的属性和特性，主存储器部分中的块的状态和高速缓存部分中块的状态。
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公开(公告)号：US20100174846A1
公开(公告)日：2010-07-08
申请号：US12348895
申请日：2009-01-05
申请人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
发明人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
CPC分类号： G06F12/0866 , G06F12/0246 , G06F12/0804 , G06F2212/7203 , G06F2212/7204 , G11C11/5628 , G11C2211/5641 , Y02D10/13
摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to archive data from the cache memory to the main memory depend on the attributes of the data to be archived, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.
摘要翻译： 将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。 缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。 在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。 将数据从高速缓冲存储器归档到主存储器的决定取决于要归档的数据的属性，主存储器部分中的块的状态和高速缓存部分中的块的状态。
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公开(公告)号：US20100172180A1
公开(公告)日：2010-07-08
申请号：US12348891
申请日：2009-01-05
申请人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
发明人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
CPC分类号： G11C11/5628 , G06F12/0246 , G06F2212/7202 , G06F2212/7203 , G11C16/0483 , G11C29/00 , G11C29/76 , G11C29/808 , G11C2211/5641 , G11C2211/5643
摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to write data to the cache memory or directly to the main memory depend on the attributes and characteristics of the data to be written, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.
摘要翻译： 将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。 缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。 在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。 将数据写入高速缓冲存储器或直接写入主存储器的决定取决于要写入的数据的属性和特性，主存储器部分中的块的状态和高速缓存部分中块的状态。
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