公开(公告)号：US20120191927A1

公开(公告)日：2012-07-26

申请号：US13433584

申请日：2012-03-29

申请人： Sergey Anatolievich Gorobets ,  Bum Suck So ,  Eugene Zilberman

发明人： Sergey Anatolievich Gorobets ,  Bum Suck So ,  Eugene Zilberman

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7208 ,  G06F2212/7211

摘要： Wear leveling techniques for re-programmable non-volatile memory systems, such as a flash EEPROM system, are described. One set of techniques uses “passive” arrangements, where, when a blocks are selected for writing, blocks with relatively low experience count are selected. This can be done by ordering the list of available free blocks based on experience count, with the “coldest” blocks placed at the front of the list, or by searching the free blocks to find a block that is “cold enough”. In another, complementary set of techniques, usable for more standard wear leveling operations as well as for “passive” techniques and other applications where the experience count is needed, the experience count of a block or meta-block is maintained as a block's attribute along its address in the data management structures, such as address tables.

摘要翻译： 描述了用于可重新编程的非易失性存储器系统（例如闪存EEPROM系统）的磨损均衡技术。 一组技术使用“被动”布置，其中当选择块用于写入时，选择具有相对较低经验计数的块。 这可以通过根据经验计数排序可用空闲块的列表，放置在列表前面的“最冷”块，或通过搜索空闲块来查找“足够冷”的块。 在另一种可用于更标准的磨损均衡操作以及需要经验计数的“被动”技术和其他应用程序的技术的补充技术中，块或元块的体验计数被保持为块的属性 其地址在数据管理结构中，如地址表。

公开(公告)号：US20100174847A1

公开(公告)日：2010-07-08

申请号：US12348899

申请日：2009-01-05

申请人： Alexander Paley ,  Sergey Anatolievich Gorobets ,  Eugene Zilberman ,  Alan David Bennett ,  Shai Traister ,  Andrew Tomlin ,  William S. Wu ,  Bum Suck So

发明人： Alexander Paley ,  Sergey Anatolievich Gorobets ,  Eugene Zilberman ,  Alan David Bennett ,  Shai Traister ,  Andrew Tomlin ,  William S. Wu ,  Bum Suck So

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/224 ,  G06F2212/7203 ,  G06F2212/7204

摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache.

摘要翻译： 将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。 缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。 在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。 响应于增加容量的需求，高速缓冲存储器具有通过从主存储器分配块而动态增加的容量。 优选地，分配耐力计数高于平均值的块。 数据的逻辑地址被划分为区域以限制高速缓存的索引的大小。

公开(公告)号：US20080235465A1

公开(公告)日：2008-09-25

申请号：US11725745

申请日：2007-03-19

申请人： Bum Suck So ,  Shai Traister

发明人： Bum Suck So ,  Shai Traister

IPC分类号： G06F12/06

CPC分类号： G06F12/0246 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0679 ,  G06F2212/7202

摘要： A non-volatile memory storage system is provided. The non-volatile memory storage system comprises a non-volatile memory cell array and a processor in communication with the non-volatile memory cell array. Here, the processor is configured to receive a write command to write data, where the write command comprises a logical address associated with the data. The processor is further configured to allocate a chaotic update block if the logical address is associated with a host file management data structure. After the allocation, the data are written to the chaotic update block.

摘要翻译： 提供了非易失性存储器存储系统。 非易失性存储器存储系统包括非易失性存储单元阵列和与非易失性存储单元阵列通信的处理器。 这里，处理器被配置为接收写入命令以写入数据，其中写入命令包括与数据相关联的逻辑地址。 处理器还被配置为如果逻辑地址与主机文件管理数据结构相关联，则分配混沌更新块。 在分配之后，数据被写入混沌更新块。

公开(公告)号：US08094500B2

公开(公告)日：2012-01-10

申请号：US12348891

申请日：2009-01-05

申请人： Alexander Paley ,  Sergey Anatolievich Gorobets ,  Eugene Zilberman ,  Alan David Bennett ,  Shai Traister ,  Andrew Tomlin ,  William S. Wu ,  Bum Suck So

发明人： Alexander Paley ,  Sergey Anatolievich Gorobets ,  Eugene Zilberman ,  Alan David Bennett ,  Shai Traister ,  Andrew Tomlin ,  William S. Wu ,  Bum Suck So

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7203 ,  G11C16/0483 ,  G11C29/00 ,  G11C29/76 ,  G11C29/808 ,  G11C2211/5641 ,  G11C2211/5643

摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to write data to the cache memory or directly to the main memory depend on the attributes and characteristics of the data to be written, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.

摘要翻译： 将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。 缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。 在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。 将数据写入高速缓冲存储器或直接写入主存储器的决定取决于要写入的数据的属性和特性，主存储器部分中的块的状态和高速缓存部分中块的状态。

公开(公告)号：US07818493B2

公开(公告)日：2010-10-19

申请号：US11851899

申请日：2007-09-07

申请人： Shai Traister ,  Bum Suck So ,  KyeYoon Park

发明人： Shai Traister ,  Bum Suck So ,  KyeYoon Park

IPC分类号： G06F13/32

CPC分类号： G06F12/0246 ,  G06F2212/7201

摘要： In a nonvolatile memory array, selected blocks are maintained as open blocks that are available to store additional data without being erased first. Nonsequential open blocks are selected from two lists, one list based on recency of the last write operation, and the other list based on frequency of writes to the block. Sequential open blocks are divided into blocks expected to remain sequential and blocks that are not expected to remain sequential.

摘要翻译： 在非易失性存储器阵列中，所选择的块被保持为可用于存储附加数据而不被首先被擦除的打开块。 从两个列表中选择非正当开放块，一个基于最后写入操作的新近的列表，另一个列表基于写入块的频率。 顺序打开的块被分成预期保持顺序的块和不预期保持顺序的块。

公开(公告)号：US20100174846A1

公开(公告)日：2010-07-08

申请号：US12348895

申请日：2009-01-05

申请人： Alexander Paley ,  Sergey Anatolievich Gorobets ,  Eugene Zilberman ,  Alan David Bennett ,  Shai Traister ,  Andrew Tomlin ,  William S. Wu ,  Bum Suck So

发明人： Alexander Paley ,  Sergey Anatolievich Gorobets ,  Eugene Zilberman ,  Alan David Bennett ,  Shai Traister ,  Andrew Tomlin ,  William S. Wu ,  Bum Suck So

IPC分类号： G06F12/02 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0866 ,  G06F12/0246 ,  G06F12/0804 ,  G06F2212/7203 ,  G06F2212/7204 ,  G11C11/5628 ,  G11C2211/5641 ,  Y02D10/13

摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to archive data from the cache memory to the main memory depend on the attributes of the data to be archived, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.

摘要翻译： 将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。 缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。 在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。 将数据从高速缓冲存储器归档到主存储器的决定取决于要归档的数据的属性，主存储器部分中的块的状态和高速缓存部分中的块的状态。

公开(公告)号：US20100172180A1

公开(公告)日：2010-07-08

申请号：US12348891

申请日：2009-01-05

申请人： Alexander Paley ,  Sergey Anatolievich Gorobets ,  Eugene Zilberman ,  Alan David Bennett ,  Shai Traister ,  Andrew Tomlin ,  William S. Wu ,  Bum Suck So

发明人： Alexander Paley ,  Sergey Anatolievich Gorobets ,  Eugene Zilberman ,  Alan David Bennett ,  Shai Traister ,  Andrew Tomlin ,  William S. Wu ,  Bum Suck So

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7203 ,  G11C16/0483 ,  G11C29/00 ,  G11C29/76 ,  G11C29/808 ,  G11C2211/5641 ,  G11C2211/5643

摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to write data to the cache memory or directly to the main memory depend on the attributes and characteristics of the data to be written, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.

摘要翻译： 将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。 缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。 在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。 将数据写入高速缓冲存储器或直接写入主存储器的决定取决于要写入的数据的属性和特性，主存储器部分中的块的状态和高速缓存部分中块的状态。

公开(公告)号：US20090070518A1

公开(公告)日：2009-03-12

申请号：US11851899

申请日：2007-09-07

申请人： Shai Traister ,  Bum Suck So ,  KyeYoon Park

发明人： Shai Traister ,  Bum Suck So ,  KyeYoon Park

IPC分类号： G06F12/06

CPC分类号： G06F12/0246 ,  G06F2212/7201

摘要： In a nonvolatile memory array, selected blocks are maintained as open blocks that are available to store additional data without being erased first. Nonsequential open blocks are selected from two lists, one list based on recency of the last write operation, and the other list based on frequency of writes to the block. Sequential open blocks are divided into blocks expected to remain sequential and blocks that are not expected to remain sequential.

摘要翻译： 在非易失性存储器阵列中，所选择的块被保持为可用于存储附加数据而不被首先被擦除的打开块。 从两个列表中选择非正当开放块，一个基于最后写入操作的新近的列表，另一个列表基于写入块的频率。 顺序打开的块被分成预期保持顺序的块和不预期保持顺序的块。

公开(公告)号：US20100174845A1

公开(公告)日：2010-07-08

申请号：US12348819

申请日：2009-01-05

申请人： Sergey Anatolievich Gorobets ,  Bum Suck So ,  Eugene Zilberman

发明人： Sergey Anatolievich Gorobets ,  Bum Suck So ,  Eugene Zilberman

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7208 ,  G06F2212/7211

摘要： Wear leveling techniques for re-programmable non-volatile memory systems, such as a flash EEPROM system, are described. One set of techniques uses “passive” arrangements, where, when a blocks are selected for writing, blocks with relatively low experience count are selected. This can be done by ordering the list of available free blocks based on experience count, with the “coldest” blocks placed at the front of the list, or by searching the free blocks to find a block that is “cold enough”. In another, complementary set of techniques, usable for more standard wear leveling operations as well as for “passive” techniques and other applications where the experience count is needed, the experience count of a block or meta-block is maintained as a block's attribute along its address in the data management structures, such as address tables.

摘要翻译： 描述了用于可重新编程的非易失性存储器系统（例如闪存EEPROM系统）的磨损均衡技术。 一组技术使用“被动”布置，其中当选择块用于写入时，选择具有相对较低经验计数的块。 这可以通过根据经验计数排序可用空闲块的列表，放置在列表前面的“最冷”块，或通过搜索空闲块来查找“足够冷”的块。 在另一种可用于更标准的磨损均衡操作以及需要经验计数的“被动”技术和其他应用程序的技术的补充技术中，块或元块的体验计数被保持为块的属性 其地址在数据管理结构中，如地址表。

公开(公告)号：US20080235439A1

公开(公告)日：2008-09-25

申请号：US11725746

申请日：2007-03-19

申请人： Bum Suck So ,  Shai Traister

发明人： Bum Suck So ,  Shai Traister

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7202

摘要： A method for operating a memory system is provided. In this method, a sequential update block is provided and a write command is received to write data. The write command comprises a logical address associated with the data. If the logical address is associated with a host file management data structure, then the sequential update block is converted to a chaotic update block. After the conversion, the data are written to the chaotic update block.

摘要翻译： 提供了一种用于操作存储器系统的方法。 在该方法中，提供顺序更新块，并且接收写入命令以写入数据。 写命令包括与数据相关联的逻辑地址。 如果逻辑地址与主机文件管理数据结构相关联，则将顺序更新块转换为混沌更新块。 转换后，将数据写入混沌更新块。