Interconnect address based QoS regulation

    公开(公告)号:US11343176B2

    公开(公告)日:2022-05-24

    申请号:US16450837

    申请日:2019-06-24

    Abstract: In various implementations, provided are systems and methods for an integrated circuit including a completer device, a requester device, and an interconnect fabric. The requester device is configured to generate transactions to the completer device, where each transaction includes a request packet that includes an attribute associated with the completer device; and the interconnect fabric is coupled to the requester device and the completer device. The integrated circuit can also include a QoS regulator configured to identify, based on a first attribute associated with the completer device, a first QoS value establishing a first priority level for a first request packet generated by the requester device, and modify the first request packet to include the first QoS value.

Patent Agency Ranking