Interconnect address based QoS regulation

    公开(公告)号:US11343176B2

    公开(公告)日:2022-05-24

    申请号:US16450837

    申请日:2019-06-24

    Abstract: In various implementations, provided are systems and methods for an integrated circuit including a completer device, a requester device, and an interconnect fabric. The requester device is configured to generate transactions to the completer device, where each transaction includes a request packet that includes an attribute associated with the completer device; and the interconnect fabric is coupled to the requester device and the completer device. The integrated circuit can also include a QoS regulator configured to identify, based on a first attribute associated with the completer device, a first QoS value establishing a first priority level for a first request packet generated by the requester device, and modify the first request packet to include the first QoS value.

    Autonomous management of communication links

    公开(公告)号:US11789807B1

    公开(公告)日:2023-10-17

    申请号:US17301254

    申请日:2021-03-30

    CPC classification number: G06F11/0793 G06F11/079 G06F11/0751

    Abstract: Systems and methods are disclosed to provide an autonomous management of communication links between dice on a multi-die assembly. Each die can include a detection unit and a controller to detect a failing communication link and perform link maintenance by directing the communication traffic on the failing link to an operational link before the link fails. Once the failing link has been repaired, the controller can re-direct the traffic back to the repaired link. The controllers on each die can negotiate through a handshake process to provide the continuous operation by switching the communication traffic from the failing link to the operational link, and then from the operational link to the repaired link.

    Scan channel fabric for tiled circuit designs

    公开(公告)号:US10990739B1

    公开(公告)日:2021-04-27

    申请号:US16366717

    申请日:2019-03-27

    Abstract: An integrated circuit device includes multiple circuit tiles disposed in a tiled arrangement in a circuit block between a first boundary and a second boundary. Each circuit tile is an instance of a circuit cell having a first edge and a second edge. The circuit cell has a scan channel circuit that includes a configurable scan channel switch and scan channels extending between the first edge and the second edge of the circuit cell through the configurable scan channel switch. Respective scan channels in the multiple circuit tiles are joined together and extend between the first boundary and the second boundary of the block of tiled arrangement. Each circuit tile can be configured to receive scan-in test data through a scan channel from either the first boundary or the second boundary, and to output scan-out result data of the circuit tile through a scan channel to either the first boundary or the second boundary.

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