公开(公告)号：US20190056885A1

公开(公告)日：2019-02-21

申请号：US16160482

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC分类号： G06F3/06 ,  G06F12/0802 ,  G06F12/1081 ,  G06N3/04

摘要： The present disclosure is directed to systems and methods of implementing a neural network using in-memory, bit-serial, mathematical operations performed by a pipelined SRAM architecture (bit-serial PISA) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. The bit-serial PISA circuitry is coupled to PISA memory circuitry via a relatively high-bandwidth connection to beneficially facilitate the storage and retrieval of layer weights by the bit-serial PISA circuitry during execution. Direct memory access (DMA) circuitry transfers the neural network model and input data from system memory to the bit-serial PISA memory and also transfers output data from the PISA memory circuitry to system memory circuitry. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of vector/tensor calculations without burdening the processor circuitry.

公开(公告)号：US20190057304A1

公开(公告)日：2019-02-21

申请号：US16160800

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC分类号： G06N3/063 ,  G06N3/04

摘要： The present disclosure is directed to systems and methods of implementing an analog neural network using a pipelined SRAM architecture (“PISA”) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. One or more physical parameters, such as a stored charge or voltage, may be used to permit the generation of an in-memory analog output using a SRAM array. The generation of an in-memory analog output using only word-line and bit-line capabilities beneficially increases the computational density of the PISA circuit without increasing power requirements. Thus, the systems and methods described herein beneficially leverage the existing capabilities of on-chip SRAM processor memory circuitry to perform a relatively large number of analog vector/tensor calculations associated with execution of a neural network, such as a recurrent neural network, without burdening the processor circuitry and without significant impact to the processor power requirements.

公开(公告)号：US20190057300A1

公开(公告)日：2019-02-21

申请号：US16160466

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC分类号： G06N3/04 ,  G06F3/06 ,  G06F12/0875

摘要： The present disclosure is directed to systems and methods of bit-serial, in-memory, execution of at least an nth layer of a multi-layer neural network in a first on-chip processor memory circuitry portion contemporaneous with prefetching and storing layer weights associated with the (n+1)st layer of the multi-layer neural network in a second on-chip processor memory circuitry portion. The storage of layer weights in on-chip processor memory circuitry beneficially decreases the time required to transfer the layer weights upon execution of the (n+1)st layer of the multi-layer neural network by the first on-chip processor memory circuitry portion. In addition, the on-chip processor memory circuitry may include a third on-chip processor memory circuitry portion used to store intermediate and/or final input/output values associated with one or more layers included in the multi-layer neural network.

公开(公告)号：US20190057036A1

公开(公告)日：2019-02-21

申请号：US16160270

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC分类号： G06F12/0875 ,  G06N3/063 ,  G06N3/04 ,  G06F3/06

摘要： The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.

公开(公告)号：US20190057050A1

公开(公告)日：2019-02-21

申请号：US16160952

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

IPC分类号： G06F13/16 ,  G06F13/28

摘要： Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.

公开(公告)号：US20190057727A1

公开(公告)日：2019-02-21

申请号：US16160955

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

IPC分类号： G11C7/10 ,  G11C5/04 ,  G06F12/06

摘要： Techniques and mechanisms for configuring a memory device to perform a sequence of in-memory computations. In an embodiment, a memory device includes a memory array and circuitry, coupled thereto, to perform data computations based on the data stored at the memory array. Based on instructions received at the memory device, control circuitry is configured to enable an automatic performance of a sequence of operations. In another embodiment, the memory device is coupled in an in-series arrangement of other memory devices to provide a pipeline circuit architecture. The memory devices each function as a respective stage of the pipeline circuit architecture, where the stages each perform respective in-memory computations. Some or all such stages each provide a different respective layer of a neural network.

公开(公告)号：US10825509B2

公开(公告)日：2020-11-03

申请号：US16146932

申请日：2018-09-28

申请人： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

发明人： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC分类号： G11C11/00 ,  G11C11/419 ,  G11C27/02 ,  G11C7/10 ,  G11C7/12 ,  G11C11/412 ,  G11C11/418

摘要： A full-rail digital-read CIM circuit enables a weighted read operation on a single row of a memory array. A weighted read operation captures a value of a weight stored in the single memory array row without having to rely on weighted row-access. Rather, using full-rail access and a weighted sampling capacitance network, the CIM circuit enables the weighted read operation even under process variation, noise and mismatch.

公开(公告)号：US20240050006A1

公开(公告)日：2024-02-15

申请号：US18367459

申请日：2023-09-13

申请人： Abhishek Sharma ,  Ahmed I. Alutaibi ,  Mohammed Alshehri ,  Sunil Kumar Sharma ,  Prateek Jain ,  Vikas Bajpai

发明人： Abhishek Sharma ,  Ahmed I. Alutaibi ,  Mohammed Alshehri ,  Sunil Kumar Sharma ,  Prateek Jain ,  Vikas Bajpai

IPC分类号： A61B5/16 ,  G16H20/00 ,  G16H50/20 ,  A61B5/00

CPC分类号： A61B5/165 ,  G16H20/00 ,  G16H50/20 ,  A61B5/7282 ,  A61B5/74

摘要： The system comprises a prediction module (1) equipped with artificial intelligence to predict neurological disorders in an individual patient and identify a level of neurological disorders; a central processing unit (2) to detect triggering events and circumstances due to which the neurological disorders trigger in an individual patient upon receiving real-time behavior information data generated by a playing ball (3) of an individual patient and distinguish between a normal behavior and a neurological disorders behavior; an alert module (4) to alert the individual patient upon determining neurological disorders behavior; and an entertainment platform (5) to entertain and engage the individual patient with a specific set of activities assigned according to detected triggering events and circumstances upon determining the neurological disorders behavior, wherein a specific set of activities includes listening to music, playing games, and talking to an AI chatbot.

公开(公告)号：US08779200B2

公开(公告)日：2014-07-15

申请号：US13203100

申请日：2010-02-25

申请人： Arun Kumar Sinha ,  Abhishek Sharma ,  Rakesh Kumar ,  Naina Sharma

发明人： Arun Kumar Sinha ,  Abhishek Sharma ,  Rakesh Kumar ,  Naina Sharma

IPC分类号： C07C241/00 ,  C07C47/00

CPC分类号： C07C45/28 ,  C07C45/30 ,  C07C249/16 ,  C07C311/49 ,  C07D317/54 ,  C07C47/228 ,  C07C47/24 ,  C07C47/23 ,  C07C47/277

摘要： The present invention provides a process for the preparation of some novel 2-aryl and 2,2-diaryl aldehydes and analogues which are privileged intermediates for commercially important nonsteroidal anti-inflammatory drugs including naproxen, flurbiprofen and potent anticancer drug candidates, including phenstatin through a unique single step synthetic methodology utilizing easily available substrates in the form of aryl alkenes as well as environmentally benign aqueous reaction conditions in the form of solvents such as mixtures of water and DMSO or Dioxane and reagents N-bromosuccinimide, N-iodosuccinimide, N-cholorosuccinimide and phase transfer catalyst such as cetyltrimethyl ammonium bromide, N-hexyl ammonium chloride for a reaction time varying from 1 min-30 min, depending upon microwave or conventional heating, without using expensive transition metal catalysts or lewis acids/bases with yield varying from 35-55%, depending upon the solvent and substrate used. The developed method provides a clean and convenient alternative to access a diverse range of medicinally important 2-aryl and 2,2-diaryl aldehyde based scaffolds in lieu of the conventional multistep protocols employing expensive and hazardous transition metal catalysts and lewis acids/bases.

摘要翻译： 本发明提供了一种制备一些新的2-芳基和2,2-二芳基醛和类似物的方法，其是用于商业上重要的非甾族抗炎药物的特权中间体，包括萘普生，氟比洛芬和有效的抗癌药物候选物，包括通过 使用易于获得的芳基烯烃底物的独特的单步合成方法以及溶剂形式的环境友好的水性反应条件，例如水和DMSO或二恶烷的混合物以及试剂N-溴琥珀酰亚胺，N-碘代琥珀酰亚胺，N-氯代氯代琥珀酰亚胺 和相转移催化剂如十六烷基三甲基溴化铵，N-己基氯化铵，反应时间为1分钟-30分钟，取决于微波或常规加热，不使用昂贵的过渡金属催化剂或路易斯酸/碱，产率从35 -55％，这取决于所用的溶剂和底物。 开发的方法提供了一种干净和方便的替代方案，以便获得各种各样的药物重要的2-芳基和2,2-二芳基醛基支架，代替常规的多步骤方案，其采用昂贵且危险的过渡金属催化剂和路易斯酸/碱。

公开(公告)号：US20130342318A1

公开(公告)日：2013-12-26

申请号：US13532826

申请日：2012-06-26

申请人： Mark P. Hinman ,  Edward Zogg ,  Abhishek Sharma

发明人： Mark P. Hinman ,  Edward Zogg ,  Abhishek Sharma

IPC分类号： G06K7/01

CPC分类号： G06K19/07327

摘要： An active RFID tag has an antenna inside RF-blocking enclosure having a port with a selected shortest dimension. An RFID reader located outside the enclosure at a reader position transmits a downlink RF signal through the port as a directional RF signal on a downlink carrier frequency corresponding to a downlink wavelength smaller than the selected shortest dimension. The port is selectively configured so that the directional downlink RF signal can pass through the port in an access mode during a selected access time interval and are attenuated by at least 60 dB in a restricted mode during a selected restricted time interval that does not overlap with the access time interval.

摘要翻译： 有源RFID标签在具有选定的最短尺寸的端口的RF阻挡外壳内具有天线。 位于读取器位置外部的RFID读取器通过端口将下行链路RF信号作为对应于小于所选择的最短维度的下行链路波长的下行链路载波上的定向RF信号来发送。 端口被选择性地配置为使得定向下行链路RF信号可以在所选择的访问时间间隔期间以访问模式通过端口，并且在受限模式期间在与第一接入时间间隔不重叠的选择的限制时间间隔期间衰减至少60dB 访问时间间隔。