公开(公告)号：US20190056885A1

公开(公告)日：2019-02-21

申请号：US16160482

申请日：2018-10-15

Applicant: Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC: G06F3/06 ,  G06F12/0802 ,  G06F12/1081 ,  G06N3/04

Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory, bit-serial, mathematical operations performed by a pipelined SRAM architecture (bit-serial PISA) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. The bit-serial PISA circuitry is coupled to PISA memory circuitry via a relatively high-bandwidth connection to beneficially facilitate the storage and retrieval of layer weights by the bit-serial PISA circuitry during execution. Direct memory access (DMA) circuitry transfers the neural network model and input data from system memory to the bit-serial PISA memory and also transfers output data from the PISA memory circuitry to system memory circuitry. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of vector/tensor calculations without burdening the processor circuitry.

公开(公告)号：US20190042159A1

公开(公告)日：2019-02-07

申请号：US16146878

申请日：2018-09-28

Applicant: Ian YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL ,  Gregory CHEN

Inventor： Ian YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL ,  Gregory CHEN

IPC: G06F3/06 ,  H03K3/03 ,  G11C7/10

Abstract: Techniques and mechanisms for a memory device to perform in-memory computing based on a logic state which is detected with a voltage-controlled oscillator (VCO). In an embodiment, a VCO circuit of the memory device receives from a memory array a first signal indicating a logic state that is based on one or more currently stored data bits. The VCO provides a conversion from the logic state being indicated by a voltage characteristic of the first signal to the logic state being indicated by a corresponding frequency characteristic of a cyclical signal. Based on the frequency characteristic, the logic state is identified and communicated for use in an in-memory computation at the memory device. In another embodiment, a result of the in-memory computation is written back to the memory array.

公开(公告)号：US20200098824A1

公开(公告)日：2020-03-26

申请号：US16142040

申请日：2018-09-26

Applicant: Abhishek SHARMA ,  Gregory K. CHEN ,  Ram KRISHNAMURTHY ,  Ravi PILLARISETTY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL ,  Urusa ALAAN ,  Noriyuki SATO

Inventor： Abhishek SHARMA ,  Gregory K. CHEN ,  Ram KRISHNAMURTHY ,  Ravi PILLARISETTY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL ,  Urusa ALAAN ,  Noriyuki SATO

IPC: H01L27/24 ,  H01L45/00

Abstract: Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a substrate, a RRAM storage cell above the substrate, and a diode adjacent to the RRAM storage cell. The RRAM storage cell includes a first electrode located in a first metal layer above the substrate, a resistive switching material layer adjacent to the first electrode, and a second electrode adjacent to the resistive switching material layer. The second electrode is shared between the RRAM storage cell and the diode. The diode includes the second electrode shared with the RRAM storage cell, a semiconductor layer adjacent to the second electrode, and a third electrode located in a second metal layer above the substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20190057304A1

公开(公告)日：2019-02-21

申请号：US16160800

申请日：2018-10-15

Applicant: Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC: G06N3/063 ,  G06N3/04

Abstract: The present disclosure is directed to systems and methods of implementing an analog neural network using a pipelined SRAM architecture (“PISA”) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. One or more physical parameters, such as a stored charge or voltage, may be used to permit the generation of an in-memory analog output using a SRAM array. The generation of an in-memory analog output using only word-line and bit-line capabilities beneficially increases the computational density of the PISA circuit without increasing power requirements. Thus, the systems and methods described herein beneficially leverage the existing capabilities of on-chip SRAM processor memory circuitry to perform a relatively large number of analog vector/tensor calculations associated with execution of a neural network, such as a recurrent neural network, without burdening the processor circuitry and without significant impact to the processor power requirements.

公开(公告)号：US20190205273A1

公开(公告)日：2019-07-04

申请号：US16146534

申请日：2018-09-28

Applicant: Jack KAVALIEROS ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory CHEN ,  Van LE ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL

Inventor： Jack KAVALIEROS ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory CHEN ,  Van LE ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL

IPC: G06F13/16 ,  H01L25/18 ,  G11C11/419 ,  G11C11/408 ,  H01L23/522 ,  H03K19/21

Abstract: Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.

公开(公告)号：US20190080731A1

公开(公告)日：2019-03-14

申请号：US16124068

申请日：2018-09-06

Applicant: Jack KAVALIEROS ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory CHEN ,  Van LE ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL

Inventor： Jack KAVALIEROS ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory CHEN ,  Van LE ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL

IPC: G11C7/10 ,  G11C11/56 ,  G11C7/18

Abstract: Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.

公开(公告)号：US20190057300A1

公开(公告)日：2019-02-21

申请号：US16160466

申请日：2018-10-15

Applicant: Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC: G06N3/04 ,  G06F3/06 ,  G06F12/0875

Abstract: The present disclosure is directed to systems and methods of bit-serial, in-memory, execution of at least an nth layer of a multi-layer neural network in a first on-chip processor memory circuitry portion contemporaneous with prefetching and storing layer weights associated with the (n+1)st layer of the multi-layer neural network in a second on-chip processor memory circuitry portion. The storage of layer weights in on-chip processor memory circuitry beneficially decreases the time required to transfer the layer weights upon execution of the (n+1)st layer of the multi-layer neural network by the first on-chip processor memory circuitry portion. In addition, the on-chip processor memory circuitry may include a third on-chip processor memory circuitry portion used to store intermediate and/or final input/output values associated with one or more layers included in the multi-layer neural network.

公开(公告)号：US20190057036A1

公开(公告)日：2019-02-21

申请号：US16160270

申请日：2018-10-15

Applicant: Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC: G06F12/0875 ,  G06N3/063 ,  G06N3/04 ,  G06F3/06

Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.