公开(公告)号：US20150180485A1

公开(公告)日：2015-06-25

申请号：US14134767

申请日：2013-12-19

Applicant: Analog Devices Technology

Inventor： Hyman Shanan ,  Michael F. Keaveney

IPC: H03L7/099 ,  H03L7/093

CPC classification number: H03L7/099 ,  H03L1/026 ,  H03L7/104

Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO having a tuning voltage input and a frequency tuning circuit configured to set a frequency band setting of the VCO. The frequency tuning circuit can include a voltage monitor configured to compare the voltage level of the tuning voltage input to one or more tuning voltage threshold levels, a control circuit configured to control at least a frequency band setting and a bias current setting of the VCO, and an amplitude detection circuit configured to compare an amplitude of an oscillation signal of the VCO to one or more amplitude threshold levels.

Abstract translation: 提供了锁相环（PLL）的频率锁定增强的装置和方法。 在一个方面，PLL可以包括具有调谐电压输入的VCO和被配置为设置VCO的频带设置的频率调谐电路。 频率调谐电路可以包括电压监视器，其被配置为将调谐电压输入的电压电平与一个或多个调谐电压阈值电平进行比较，控制电路被配置为至少控制VCO的频带设置和偏置电流设置， 以及振幅检测电路，被配置为将VCO的振荡信号的振幅与一个或多个振幅阈值电平进行比较。

公开(公告)号：US20150180486A1

公开(公告)日：2015-06-25

申请号：US14134782

申请日：2013-12-19

Applicant: Analog Devices Technology

Inventor： Hyman Shanan ,  Michael F. Keaveney

IPC: H03L7/099 ,  H03L7/085

CPC classification number: H03L7/099 ,  H03L1/026 ,  H03L7/085 ,  H03L7/104

Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO and a calibration voltage generation circuit that can generate a calibration voltage for controlling a tuning voltage input of the VCO when the VCO is being coarsely tuned. Additionally, the calibration voltage generation circuit can sense a temperature of the PLL, and can control a voltage level of the calibration voltage to provide compensation based on the sensed temperature. The calibration voltage generation circuit can include a bandgap reference circuit configured to generate a zero-to-absolute-temperature (ZTAT) current and a proportional-to-absolute temperature (PTAT) current, and the calibration voltage can be generated based in part on a difference between the PTAT current and the ZTAT current.

Abstract translation: 提供了锁相环（PLL）的频率锁定增强的装置和方法。 在一个方面，PLL可以包括VCO和校准电压产生电路，当VCO被粗调谐时，可以产生用于控制VCO的调谐电压输入的校准电压。 此外，校准电压产生电路可以感测PLL的温度，并且可以控制校准电压的电压电平，以基于感测到的温度来提供补偿。 校准电压产生电路可以包括被配置为产生零绝对温度（ZTAT）电流和比例绝对温度（PTAT）电流的带隙基准电路，并且校准电压可以部分地基于 PTAT电流和ZTAT电流之间的差异。

公开(公告)号：US20150084676A1

公开(公告)日：2015-03-26

申请号：US14034917

申请日：2013-09-24

Applicant: Analog Devices Technology

Inventor： David J. McLaurin ,  Christopher W. Angell ,  Michael F. Keaveney

IPC: H03L7/085 ,  H03L7/10

CPC classification number: H03L7/1976 ,  H03L7/085 ,  H03L7/104 ,  H03L7/199 ,  H03L7/23

Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.