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    SYSTEMS, METHODS, AND DEVICES FOR OUT-OF-ORDER DELIVERY WITH MULTIPLE RLC ENTITIES
    2.
    发明公开
    SYSTEMS, METHODS, AND DEVICES FOR OUT-OF-ORDER DELIVERY WITH MULTIPLE RLC ENTITIES 审中-公开

    公开(公告)号：US20240284239A1

    公开(公告)日：2024-08-22

    申请号：US18415103

    申请日：2024-01-17

    Applicant: Apple Inc.

    Inventor： Ralf Rossbach ,  Fangli Xu ,  Bobby Jose ,  Ping-Heng Kuo ,  Vijay Venkataraman ,  Haijing Hu

    IPC: H04W28/02

    CPC classification number: H04W28/0252

    Abstract: The techniques described herein may include a device, comprising: a memory; and one or more processors configured to, when executing instructions stored in the memory, cause the device to: communicate, via a wireless communication network, information as in-order traffic using an in-order radio link control (RLC) entity; and communicate, via the wireless communication network, information as out-of-order traffic using an out-of-order RLC entity. The in-order traffic and the out-of-order traffic may be communicated using the same data radio bearer (DRB). The out-of-order traffic may include selective out-of-order delivery (OOD) or per-packet OOD. Additional examples, features and other techniques are also described herein.

    DYNAMIC L2 BUFFER SCALING
    7.
    发明公开
    DYNAMIC L2 BUFFER SCALING 审中-公开

    公开(公告)号：US20240064560A1

    公开(公告)日：2024-02-22

    申请号：US17890408

    申请日：2022-08-18

    Applicant: Apple Inc.

    Inventor： Abhishek Anand Konda ,  Bobby Jose ,  Vijay Venkataraman

    IPC: H04W28/02

    CPC classification number: H04W28/0278 ,  H04W28/0247

    Abstract: Systems, methods, and circuitries are provided for using an application Layer 2 buffer for reordering out of sequence (OOS) packets when possible to reduce an amount of memory allocated to a baseband (BB) Layer 2 (L2) buffer. In one example, a baseband circuitry of a user equipment (UE), includes BB memory, configured as a BB L2 buffer and one or more BB processors. The BB processors are configured to receive an OOS packet from a physical layer; and in response to an APP L2 buffer status indicating at least a first amount of memory is available, send the OOS packet to APP circuitry for storing in an APP L2 buffer.

    Systems and Methods for Balancing Loads Across Multiple Processing Cores of a Wireless Device
    8.
    发明公开
    Systems and Methods for Balancing Loads Across Multiple Processing Cores of a Wireless Device 审中-公开

    公开(公告)号：US20230195530A1

    公开(公告)日：2023-06-22

    申请号：US17951031

    申请日：2022-09-22

    Applicant: Apple Inc.

    Inventor： Santosh Abraham ,  Vijay Venkataraman ,  Bobby Jose

    IPC: G06F9/50 ,  G06F16/21

    CPC classification number: G06F9/505 ,  G06F16/211

    Abstract: In an example method, a system obtains a data packet for processing, determines a hash value representing the data packet, and selects a processor core from among a plurality of processor cores for processing the data packet. The processor core is selected by determining, based on the hash value, that the hash value corresponds to a first processor core from among the plurality of processor cores, and determining, based on a plurality of data structures stored by the load balancing system, whether to select the first processor core or a second processor core from among the plurality of processor cores for processing the data packet. Further, the system causes the selected processor core to process the data packet.

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