公开(公告)号：US11609270B2

公开(公告)日：2023-03-21

申请号：US17882657

申请日：2022-08-08

Applicant: Apple Inc.

Inventor： FNU Rajeev Kumar ,  Chandan Shantharaj

IPC: G01R31/3185 ,  G01R31/3177

Abstract: An Integrated Circuit (IC) includes a storage element and control circuitry. The control circuitry is configured to select, responsively to a scan-enable control, between a functional-data input and a scan-data input to serve as an input to the storage element, to selectively disable toggling of an output of the storage element, responsively to a clock-enable control, by gating a clock signal provided to the storage element, and, while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, to select the input of the storage element to be the scan-data input.

公开(公告)号：US20230019009A1

公开(公告)日：2023-01-19

申请号：US17882657

申请日：2022-08-08

Applicant: Apple Inc.

Inventor： FNU Rajeev Kumar ,  Chandan Shantharaj

IPC: G01R31/3185 ,  G01R31/3177

Abstract: An Integrated Circuit (IC) includes a storage element and control circuitry. The control circuitry is configured to select, responsively to a scan-enable control, between a functional-data input and a scan-data input to serve as an input to the storage element, to selectively disable toggling of an output of the storage element, responsively to a clock-enable control, by gating a clock signal provided to the storage element, and, while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, to select the input of the storage element to be the scan-data input.

公开(公告)号：US11893241B1

公开(公告)日：2024-02-06

申请号：US17823695

申请日：2022-08-31

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Sandeep Gupta ,  Chandan Shantharaj ,  Krishna C. Potnuru ,  Sahil Kapoor

IPC: G06F3/06 ,  G06F12/0877

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0877 ,  G06F2212/60

Abstract: A variable latency cache memory is disclosed. A cache subsystem includes a pipeline control circuit configured to initiate cache memory accesses for data. The cache subsystem further includes a cache memory circuit having a data array arranged into a plurality of groups, wherein different ones of the plurality of groups have different minimum access latencies due to different distances from the pipeline control circuit. A plurality of latency control circuits configured to ensure a latency is bounded to a maximum value for a given access to the data array, wherein a given latency control circuit is associated with a corresponding group of the plurality of groups. The latency for a given access may thus vary between a minimum access latency for a group closest to the pipeline control circuit to a maximum latency for an access to the group furthest from the pipeline control circuit.

公开(公告)号：US20230194606A1

公开(公告)日：2023-06-22

申请号：US18169894

申请日：2023-02-16

Applicant: APPLE INC.

Inventor： FNU Rajeev Kumar ,  Chandan Shantharaj

IPC: G01R31/3185 ,  G01R31/3177

CPC classification number: G01R31/318536 ,  G01R31/3177 ,  G01R31/318541 ,  G01R31/318552 ,  G01R31/318572

Abstract: An Integrated Circuit (IC) includes a storage element and control circuitry. The control circuitry is configured to select, responsively to a scan-enable control, between a functional-data input and a scan-data input to serve as an input to the storage element, to selectively disable toggling of an output of the storage element, responsively to a clock-enable control, by gating a clock signal provided to the storage element, and, while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, to select the input of the storage element to be the scan-data input.

公开(公告)号：US11454671B1

公开(公告)日：2022-09-27

申请号：US17363093

申请日：2021-06-30

Applicant: Apple Inc.

Inventor： FNU Rajeev Kumar ,  Chandan Shantharaj

IPC: G01R31/3185 ,  G01R31/3177

Abstract: An Integrated Circuit (IC) includes a storage element and control circuitry. The control circuitry is configured to select, responsively to a scan-enable control, between a functional-data input and a scan-data input to serve as an input to the storage element, to selectively disable toggling of an output of the storage element, responsively to a clock-enable control, by gating a clock signal provided to the storage element, and, while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, to select the input of the storage element to be the scan-data input.