公开(公告)号：US12132581B2

公开(公告)日：2024-10-29

申请号：US17103802

申请日：2020-11-24

申请人： Intel Corporation

发明人： Sujoy Sen ,  Durgesh Srivastava ,  Thomas E. Willis ,  Bassam N. Coury ,  Marcelo Cintra

IPC分类号： H04L12/18 ,  G06F12/02 ,  G06F12/0813 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  H04L12/54 ,  H04L45/74 ,  H04L49/201 ,  H04L67/1095 ,  H04L12/70

CPC分类号： H04L12/1868 ,  G06F12/0238 ,  G06F12/0813 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/1689 ,  G06F13/28 ,  G06F13/4059 ,  H04L12/5601 ,  H04L45/74 ,  H04L49/201 ,  H04L67/1095 ,  G06F2213/28 ,  H04L2012/562

摘要： Examples described herein includes an apparatus comprising: a network interface configured to: receive a request to copy data from a local memory to a remote memory; based on a configuration that the network interface is to manage a cache store the data into the cache and record that the data is stored in the cache. In some examples, store the data in the cache comprises store most recently evicted data from the local memory into the cache. In some examples, the network interface is to store data evicted from the local memory that is not stored into the cache into one or more remote memories.

公开(公告)号：US12111767B2

公开(公告)日：2024-10-08

申请号：US18302968

申请日：2023-04-19

申请人： Advanced Micro Devices, Inc.

发明人： Susumu Mashimo ,  John Kalamatianos

IPC分类号： G06F12/0862 ,  G06F9/30 ,  G06F12/0877 ,  G06F18/214

CPC分类号： G06F12/0862 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30101 ,  G06F12/0877 ,  G06F18/214 ,  G06F2212/6024

摘要： A method includes recording a first set of consecutive memory access deltas, where each of the consecutive memory access deltas represents a difference between two memory addresses accessed by an application, updating values in a prefetch training table based on the first set of memory access deltas, and predicting one or more memory addresses for prefetching responsive to a second set of consecutive memory access deltas and based on values in the prefetch training table.

公开(公告)号：US20240320156A1

公开(公告)日：2024-09-26

申请号：US18588532

申请日：2024-02-27

申请人： Imagination Technologies Limited

发明人： Ross Martin Torkington

IPC分类号： G06F12/0877

CPC分类号： G06F12/0877

摘要： A device in which each field in a first RAM together with a respective field in a second RAM form a respective entry of a cache RAM. Caching circuitry is operable to use the respective field in the first RAM to hold a first portion of a single cacheline, and the respective field in the second RAM to hold the corresponding tag of the single cacheline and a remaining portion of the single cacheline. The caching circuitry is further arranged so as, upon a cache hit by a subsequent memory access operation requesting to access data for which a corresponding cacheline has already been cached, to retrieve the corresponding tag and the remaining portion of the respective cacheline from the second RAM in a first one of a sequence of clock cycles.

公开(公告)号：US20240320155A1

公开(公告)日：2024-09-26

申请号：US18588289

申请日：2024-02-27

申请人： Imagination Technologies Limited

发明人： Ross Martin Torkington

IPC分类号： G06F12/0877 ,  G06F12/0895

CPC分类号： G06F12/0877 ,  G06F12/0895

摘要： A device in which each field in a first RAM together with a respective field in a second RAM form a respective entry of a cache RAM. Caching circuitry is operable to select between applying a first mode and a second mode in at least one entry in the cache RAM. In the first mode, the respective field in the first RAM is used to hold a first portion of a single cacheline in a first format, and the respective field in the second RAM is used to hold the corresponding tag of the single cacheline and a remaining portion of the single cacheline. In the second mode, the first RAM is used to hold a plural cachelines in a second format shorter than the first format, and the corresponding entry in the second RAM is used to hold the corresponding tags of the plural cachelines.

公开(公告)号：US20240264944A1

公开(公告)日：2024-08-08

申请号：US18432518

申请日：2024-02-05

申请人： Micron Technology, Inc.

发明人： Luca Bert

IPC分类号： G06F12/0877 ,  G06F12/0815 ,  G06F12/123

CPC分类号： G06F12/0877 ,  G06F12/0815 ,  G06F12/123

摘要： A computing device having a computer express link (CXL) connection between a memory sub-system and a host system and having storage access queues configured at least in part in the memory sub-system. The memory sub-system can attach, as a memory device, a portion of its fast random access memory over the connection to the host system. One or more storage access queues can be configured in the memory device. The host system can use a cache-coherent memory access protocol to communicate storage access messages over the connection to the random access memory of the memory sub-system. Optionally, the host system can have a memory with second storage access queues usable to access the storage services of the memory sub-system over the connection using a storage access protocol.

公开(公告)号：US11966336B2

公开(公告)日：2024-04-23

申请号：US17521707

申请日：2021-11-08

申请人： SAP SE

发明人： Debashis Banerjee ,  Prateek Agarwal ,  Kavitha Krishnan

IPC分类号： G06F12/0837 ,  G06F12/0877

CPC分类号： G06F12/0837 ,  G06F12/0877

摘要： Some embodiments provide a program that receives a first set of data and a first greenhouse gas emission value. The program stores, in a cache, the first set of data and the first greenhouse gas emission value. The program receives a second set of data and a second greenhouse gas emission value. The program stores, in the cache, the second set of data and the second greenhouse gas emission value. The program receives a third set of data and a third greenhouse gas emission value. The program determines one of the first and second sets of data to remove from the cache based on the first and second greenhouse gas emission values. The program replaces, in the cache, one of the first and second sets of data and the corresponding first or second greenhouse gas emission value with the third set of data and the third greenhouse gas emission value.

公开(公告)号：US20240111677A1

公开(公告)日：2024-04-04

申请号：US17957795

申请日：2022-09-30

申请人： Advanced Micro Devices, Inc.

发明人： Gabriel H. Loh ,  Marko Scrbak ,  Akhil Arunkumar ,  John Kalamatianos

IPC分类号： G06F12/0862 ,  G06F12/0877

CPC分类号： G06F12/0862 ,  G06F12/0877 ,  G06F12/0811

摘要： A method for performing prefetching operations is disclosed. The method includes storing a recorded access pattern indicating a set of accesses for a region; in response to an access within the region, fetching the recorded access pattern; and performing prefetching based on the access pattern.

公开(公告)号：US11934311B2

公开(公告)日：2024-03-19

申请号：US17736557

申请日：2022-05-04

申请人： NVIDIA CORPORATION

发明人： Michael Fetterman ,  Steven James Heinrich ,  Shirish Gadre

IPC分类号： G06F12/00 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0877

CPC分类号： G06F12/0811 ,  G06F9/3816 ,  G06F12/084 ,  G06F12/0877

摘要： Various embodiments include a system for managing cache memory in a computing system. The system includes a sectored cache memory that provides a mechanism for sharing sectors in a cache line among multiple cache line allocations. Traditionally, different cache line allocations are assigned to different cache lines in the cache memory. Further, cache line allocations may not use all of the sectors of the cache line, leading to low utilization of the cache memory. With the present techniques, multiple cache lines share the same cache line, leading to improved cache memory utilization relative to prior techniques. Further, sectors of cache allocations can be assigned to reduce data bank conflicts when accessing cache memory. Reducing such data bank conflicts can result in improved memory access performance, even when cache lines are shared with multiple allocations.

公开(公告)号：US11868264B2

公开(公告)日：2024-01-09

申请号：US18168157

申请日：2023-02-13

申请人： Intel Corporation

发明人： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC分类号： G06F12/0877 ,  G06F12/0802 ,  G06F12/0855 ,  G06F12/0806 ,  G06F12/0846 ,  G06F12/0868 ,  G06T1/60 ,  G06F12/126 ,  G06F12/0893

CPC分类号： G06F12/0877 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0848 ,  G06F12/0855 ,  G06F12/0868 ,  G06F12/126 ,  G06T1/60 ,  G06F12/0893

摘要： One embodiment provides circuitry coupled with cache memory and a memory interface, the circuitry to compress compute data at multiple cache line granularity, and a processing resource coupled with the memory interface and the cache memory. The processing resource is configured to perform a general-purpose compute operation on compute data associated with multiple cache lines of the cache memory. The circuitry is configured to compress the compute data before a write of the compute data via the memory interface to the memory bus, in association with a read of the compute data associated with the multiple cache lines via the memory interface, decompress the compute data, and provide the decompressed compute data to the processing resource.

公开(公告)号：US20230281129A1

公开(公告)日：2023-09-07

申请号：US18066061

申请日：2022-12-14

申请人： Fujitsu Limited

发明人： Ken IIZAWA

IPC分类号： G06F12/084 ,  G06F12/0877 ,  G06N5/04

CPC分类号： G06F12/084 ,  G06F12/0877 ,  G06N5/04

摘要： An information processing apparatus includes: calculation circuits that each executes deep learning; a shared memory that is shared by the calculation circuits; an access information memory that holds, for each of the calculation circuits, a write request for writing data generated in forward propagation processing by the calculation circuits to the shared memory, a read request for reading the data used in backward propagation processing by the calculation circuits from the shared memory, and a start time of backward propagation processing; and a processor that schedules data transfer between the calculation circuits and the shared memory based on the write request, the read request, and the start time of backward propagation processing such that the data is transferred from the shared memory to a calculation circuit that executes backward propagation processing by the start time of backward propagation processing, and accesses the shared memory based on a scheduling result.