公开(公告)号：US20200341533A1

公开(公告)日：2020-10-29

申请号：US16397888

申请日：2019-04-29

Applicant: Apple Inc.

Inventor： Ching Elizabeth Ho ,  Hao Chen ,  Nitin Bhargava ,  Syed F. Ali

IPC: G06F1/329 ,  G06F1/3228

Abstract: An apparatus includes a plurality of processor cores, a cache memory that includes a plurality of banks, and a power management circuit. The power management circuit is configured to maintain a power credit approach for the apparatus that includes tracking a total number of currently available power credits, and to store a plurality of threshold values. Each threshold value is associated with one or more of a plurality of throttling actions. In response to the total number of currently available power credits reaching a particular threshold value of the plurality of threshold values, the power management circuit performs the one or more throttling actions associated with the particular threshold value. The plurality of throttling actions includes selectively throttling one or more of the plurality of processor cores, and selectively throttling one or more of the plurality of banks in the cache memory.

公开(公告)号：US11048323B2

公开(公告)日：2021-06-29

申请号：US16397888

申请日：2019-04-29

Applicant: Apple Inc.

Inventor： Ching Elizabeth Ho ,  Hao Chen ,  Nitin Bhargava ,  Syed F. Ali

IPC: G06F1/329 ,  G06F1/3228

Abstract: An apparatus includes a plurality of processor cores, a cache memory that includes a plurality of banks, and a power management circuit. The power management circuit is configured to maintain a power credit approach for the apparatus that includes tracking a total number of currently available power credits, and to store a plurality of threshold values. Each threshold value is associated with one or more of a plurality of throttling actions. In response to the total number of currently available power credits reaching a particular threshold value of the plurality of threshold values, the power management circuit performs the one or more throttling actions associated with the particular threshold value. The plurality of throttling actions includes selectively throttling one or more of the plurality of processor cores, and selectively throttling one or more of the plurality of banks in the cache memory.