公开(公告)号：US09405604B2

公开(公告)日：2016-08-02

申请号：US14253150

申请日：2014-04-15

Applicant: Apple Inc.

Inventor： Nitin Bhargava

IPC: G06F13/12 ,  G06F9/45 ,  G06F11/00 ,  G01R31/317 ,  G06F11/22

CPC classification number: G06F11/00 ,  G01R31/31705 ,  G06F11/22 ,  G06F11/267

Abstract: An integrated circuit (IC) having a debug access port coupled to a processing circuit without a dedicated sideband interface is disclosed. In one embodiment, an IC includes a processor circuit and a DAP. The IC also includes a communications fabric over which communications transactions may be conveyed between the various functional circuits of the IC using a fabric protocol. Both the DAP and the processing circuit are coupled to the communications fabric. The IC also includes a translation circuit coupled between the processing circuit and the communications fabric. The translation circuit may translate transactions conveyed between the processing circuit and the DAP from or to a debug protocol to or from the fabric protocol. Thus, the DAP and the processing circuit may communicate according to the debug protocol without a dedicated sideband coupled therebetween.

Abstract translation: 公开了一种具有与没有专用边带接口的处理电路耦合的调试访问端口的集成电路（IC）。 在一个实施例中，IC包括处理器电路和DAP。 IC还包括通信结构，通过该通信结构，可以使用结构协议在IC的各个功能电路之间传送通信事务。 DAP和处理电路都耦合到通信结构。 IC还包括耦合在处理电路和通信结构之间的转换电路。 翻译电路可以将在处理电路和DAP之间传送的交易从或从架构协议转换到调试协议。 因此，DAP和处理电路可以根据调试协议通信，而不在其间耦合专用边带。

公开(公告)号：US11048323B2

公开(公告)日：2021-06-29

申请号：US16397888

申请日：2019-04-29

Applicant: Apple Inc.

Inventor： Ching Elizabeth Ho ,  Hao Chen ,  Nitin Bhargava ,  Syed F. Ali

IPC: G06F1/329 ,  G06F1/3228

Abstract: An apparatus includes a plurality of processor cores, a cache memory that includes a plurality of banks, and a power management circuit. The power management circuit is configured to maintain a power credit approach for the apparatus that includes tracking a total number of currently available power credits, and to store a plurality of threshold values. Each threshold value is associated with one or more of a plurality of throttling actions. In response to the total number of currently available power credits reaching a particular threshold value of the plurality of threshold values, the power management circuit performs the one or more throttling actions associated with the particular threshold value. The plurality of throttling actions includes selectively throttling one or more of the plurality of processor cores, and selectively throttling one or more of the plurality of banks in the cache memory.

公开(公告)号：US20200341533A1

公开(公告)日：2020-10-29

申请号：US16397888

申请日：2019-04-29

Applicant: Apple Inc.

Inventor： Ching Elizabeth Ho ,  Hao Chen ,  Nitin Bhargava ,  Syed F. Ali

IPC: G06F1/329 ,  G06F1/3228

Abstract: An apparatus includes a plurality of processor cores, a cache memory that includes a plurality of banks, and a power management circuit. The power management circuit is configured to maintain a power credit approach for the apparatus that includes tracking a total number of currently available power credits, and to store a plurality of threshold values. Each threshold value is associated with one or more of a plurality of throttling actions. In response to the total number of currently available power credits reaching a particular threshold value of the plurality of threshold values, the power management circuit performs the one or more throttling actions associated with the particular threshold value. The plurality of throttling actions includes selectively throttling one or more of the plurality of processor cores, and selectively throttling one or more of the plurality of banks in the cache memory.

公开(公告)号：US20150092854A1

公开(公告)日：2015-04-02

申请号：US14039729

申请日：2013-09-27

Applicant: Apple Inc.

Inventor： James E. Orr ,  Timothy John Millet ,  Joseph J. Cheng ,  Nitin Bhargava ,  Guy Cote

IPC: H04N19/436 ,  H04N19/433 ,  H04N19/51 ,  H04N19/583 ,  H04N19/43

CPC classification number: H04N19/43 ,  G06T1/20 ,  H04N19/433 ,  H04N19/436 ,  H04N19/51 ,  H04N19/513

Abstract: A block processing pipeline that includes a software pipeline and a hardware pipeline that run in parallel. The software pipeline runs at least one block ahead of the hardware pipeline. The stages of the pipeline may each include a hardware pipeline component that performs one or more operations on a current block at the stage. At least one stage of the pipeline may also include a software pipeline component that determines a configuration for the hardware component at the stage of the pipeline for processing a next block while the hardware component is processing the current block. The software pipeline component may determine the configuration according to information related to the next block obtained from an upstream stage of the pipeline. The software pipeline component may also obtain and use information related to a block that was previously processed at the stage.

Abstract translation: 一个块处理流水线，包括一个软件流水线和并行运行的硬件流水线。 软件管道在硬件管道之前至少运行一个程序段。 流水线的各个阶段可以各自包括在该阶段对当前块执行一个或多个操作的硬件流水线组件。 管道的至少一个阶段还可以包括软件流水线组件，该软件流水线组件在硬件组件正在处理当前块时，在流水线阶段确定用于处理下一个块的硬件组件的配置。 软件管线组件可以根据从流水线的上游级获得的与下一块相关的信息来确定配置。 软件管道组件还可以获得并使用与先前在该阶段处理的块相关的信息。

公开(公告)号：US09215472B2

公开(公告)日：2015-12-15

申请号：US14039729

申请日：2013-09-27

Applicant: Apple Inc.

Inventor： James E. Orr ,  Timothy John Millet ,  Joseph J. Cheng ,  Nitin Bhargava ,  Guy Cote

IPC: G06T1/20 ,  G06T1/00 ,  G06F15/00 ,  H04N19/43 ,  H04N19/433 ,  H04N19/436 ,  H04N19/51 ,  H04N19/583 ,  H04N19/513

CPC classification number: H04N19/43 ,  G06T1/20 ,  H04N19/433 ,  H04N19/436 ,  H04N19/51 ,  H04N19/513

Abstract: A block processing pipeline that includes a software pipeline and a hardware pipeline that run in parallel. The software pipeline runs at least one block ahead of the hardware pipeline. The stages of the pipeline may each include a hardware pipeline component that performs one or more operations on a current block at the stage. At least one stage of the pipeline may also include a software pipeline component that determines a configuration for the hardware component at the stage of the pipeline for processing a next block while the hardware component is processing the current block. The software pipeline component may determine the configuration according to information related to the next block obtained from an upstream stage of the pipeline. The software pipeline component may also obtain and use information related to a block that was previously processed at the stage.

Abstract translation: 一个块处理流水线，包括一个软件流水线和并行运行的硬件流水线。 软件管道在硬件管道之前至少运行一个程序段。 流水线的各个阶段可以各自包括在该阶段对当前块执行一个或多个操作的硬件流水线组件。 管道的至少一个阶段还可以包括软件流水线组件，该软件流水线组件在硬件组件正在处理当前块时，在流水线阶段确定用于处理下一个块的硬件组件的配置。 软件管线组件可以根据从流水线的上游级获得的与下一块相关的信息来确定配置。 软件管道组件还可以获得并使用与先前在该阶段处理的块相关的信息。

公开(公告)号：US09454378B2

公开(公告)日：2016-09-27

申请号：US14083010

申请日：2013-11-18

Applicant: Apple Inc.

Inventor： Guy Cote ,  Joseph P. Bratt ,  Nitin Bhargava ,  Hao Chen ,  Joseph J. Cheng

IPC: G06F3/00 ,  G06F13/00 ,  G06F9/44 ,  G06F3/06 ,  G06F9/445

CPC classification number: G06F9/4401 ,  G06F3/0629 ,  G06F8/71 ,  G06F9/445

Abstract: Methods and apparatus for configuring multiple components of a subsystem are described. The configuration memory of each of a plurality of components coupled to an interconnect includes a global configuration portion. The configuration memory of one of the components may be designated as a master global configuration for all of the components. A module coupled to the interconnect may receive writes to the components from a configuration source. For each write, the module may decode the write to determine addressing information and check to see if the write is addressed to the master global configuration. If the write is addressed to the master global configuration, the module broadcasts the write to the global configuration portion of each of the components via the interconnect. If the write is not addressed to the master global configuration, the module forwards the write to the appropriate component via the interconnect.

Abstract translation: 描述用于配置子系统的多个组件的方法和装置。 耦合到互连的多个组件中的每一个的配置存储器包括全局配置部分。 可以将组件之一的配置存储器指定为用于所有组件的主全局配置。 耦合到互连的模块可以从配置源接收对组件的写入。 对于每次写入，模块可以解码写入以确定寻址信息，并检查写入是否寻址到主全局配置。 如果写入寻址到主全局配置，则模块通过互连广播写入每个组件的全局配置部分。 如果写入不适用于主全局配置，则模块通过互连将写入转发到相应的组件。

公开(公告)号：US20150293172A1

公开(公告)日：2015-10-15

申请号：US14253150

申请日：2014-04-15

Applicant: Apple Inc.

Inventor： Nitin Bhargava

IPC: G01R31/3177

CPC classification number: G06F11/00 ,  G01R31/31705 ,  G06F11/22 ,  G06F11/267

Abstract: An integrated circuit (IC) having a debug access port coupled to a processing circuit without a dedicated sideband interface is disclosed. In one embodiment, an IC includes a processor circuit and a DAP. The IC also includes a communications fabric over which communications transactions may be conveyed between the various functional circuits of the IC using a fabric protocol. Both the DAP and the processing circuit are coupled to the communications fabric. The IC also includes a translation circuit coupled between the processing circuit and the communications fabric. The translation circuit may translate transactions conveyed between the processing circuit and the DAP from or to a debug protocol to or from the fabric protocol. Thus, the DAP and the processing circuit may communicate according to the debug protocol without a dedicated sideband coupled therebetween.

Abstract translation: 公开了一种具有与没有专用边带接口的处理电路耦合的调试访问端口的集成电路（IC）。 在一个实施例中，IC包括处理器电路和DAP。 IC还包括通信结构，通过该通信结构，可以使用结构协议在IC的各种功能电路之间传送通信事务。 DAP和处理电路都耦合到通信结构。 IC还包括耦合在处理电路和通信结构之间的转换电路。 翻译电路可以将在处理电路和DAP之间传送的交易从或从架构协议转换到调试协议。 因此，DAP和处理电路可以根据调试协议通信，而不在其间耦合专用边带。

公开(公告)号：US20150095630A1

公开(公告)日：2015-04-02

申请号：US14083010

申请日：2013-11-18

Applicant: Apple Inc.

Inventor： Guy Cote ,  Joseph P. Bratt ,  Nitin Bhargava ,  Hao Chen ,  Joseph J. Cheng

IPC: G06F9/44

CPC classification number: G06F9/4401 ,  G06F3/0629 ,  G06F8/71 ,  G06F9/445

Abstract: Methods and apparatus for configuring multiple components of a subsystem are described. The configuration memory of each of a plurality of components coupled to an interconnect includes a global configuration portion. The configuration memory of one of the components may be designated as a master global configuration for all of the components. A module coupled to the interconnect may receive writes to the components from a configuration source. For each write, the module may decode the write to determine addressing information and check to see if the write is addressed to the master global configuration. If the write is addressed to the master global configuration, the module broadcasts the write to the global configuration portion of each of the components via the interconnect. If the write is not addressed to the master global configuration, the module forwards the write to the appropriate component via the interconnect.

Abstract translation: 描述用于配置子系统的多个组件的方法和装置。 耦合到互连的多个组件中的每一个的配置存储器包括全局配置部分。 可以将组件之一的配置存储器指定为用于所有组件的主全局配置。 耦合到互连的模块可以从配置源接收对组件的写入。 对于每次写入，模块可以解码写入以确定寻址信息，并检查写入是否寻址到主全局配置。 如果写入寻址到主全局配置，则模块通过互连广播写入每个组件的全局配置部分。 如果写入不适用于主全局配置，则模块通过互连将写入转发到相应的组件。